Intel Core 2 Duo Processor and Intel Q35 Express
Table 1. | Definition | (Sheet 2 of 2) | |
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| Term |
| Description |
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| Advanced Digital Display Card – 2nd Generation. This card provides digital display options |
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| for an Intel Graphics Controller that supports ADD2+ cards. It plugs into a x16 PCI |
| ADD2 Card |
| Express* connector but uses the multiplexed SDVO interface. The card adds Video In |
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| capabilities to platform. This Advanced Digital Display Card will not work with an Intel | |
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| Graphics Controller that supports DVO and ADD cards. It will function as an ADD2 card in |
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| an ADD2 supported system, but video in capabilities will not work. |
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| Memory Controller Hub component that contains the processor interface, DRAM |
| MCH |
| controller, and x16 PCI Express* port (typically, the external graphics interface). It |
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| communicates with the I/O controller hub (Intel ICH9) and other I/O controller hubs over | |
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| the DMI interconnect. In this document MCH refers to the Intel® Q35 MCH component. |
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| MEC |
| Media Expansion Card, also known as ADD2+ card. Refer to ADD2+ term for description. |
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| Third Generation input/output graphics attach called PCI Express* Graphics. PCI Express* |
| PCI Express* |
| is a |
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| existing PCI specifications. The specific PCI Express* implementation intended for | |
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| connecting the (G)MCH to an external Graphics Controller is a x16 link and replaces AGP. |
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| The Primary PCI is the physical PCI bus that is driven directly by the ICH9 component. |
| Primary PCI |
| Communication between Primary PCI and the (G)MCH occurs over DMI. Note that the |
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| Primary PCI bus is not PCI Bus 0 from a configuration standpoint. |
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| Serial Digital Video Out (SDVO). SDVO is a digital display channel that serially transmits |
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| digital display data to an external SDVO device. The SDVO device accepts this serialized |
| SDVO |
| format and then translates the data into the appropriate display format (i.e., TMDS, |
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| LVDS, | |
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| display channel - DVO. For the 82Q965 GMCH, it will be multiplexed on a portion of the |
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| x16 graphics PCI Express* interface. |
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| SDVO Device |
| Third party codec that uses SDVO as an input. May have a variety of output formats, |
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| including DVI, LVDS, HDMI, | |
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| System Management Interrupt. SMI is used to indicate any of several system conditions |
| SMI |
| (such as, thermal sensor events, throttling activated, access to System Management |
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| RAM, chassis open, or other system state related activity). |
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| A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four x16 SDRAM |
| Rank |
| devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a |
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| single side of a DIMM. |
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1.4Support Options
1.4.1Electronic Support Systems
Intel’s site on the World Wide Web (http://www.intel.com/) provides
Product documentation is provided online in a variety of
(http://developer.intel.com/)
1.4.2Additional Technical Support
If you require additional technical support, please contact your field sales representative or local distributor.
1.5Product Literature
Product literature can be ordered from the following Intel literature centers:
Intel® CoreTM 2 Duo Processor and Intel ® Q35 Express Chipset Development Kit |
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User’s Manual | October 2007 |
8 | Order Number: 318476001US |