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Intel IQ80960RM, RN 3.4 Console Serial Port, 3.5 Secondary PCI Bus Expansion Connectors

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3-4 IQ80960RM/RN

Evaluation Board Manual

Hardware Reference

3.4 Console Serial Port

The console serial port on the IQ80960RM/RN platform, based on a 16C550 UART, is capable of

operation from 300 to 115,200 bps. The port is connected to a phone jack-style plug on the

IQ80960RM/RN platform. The DB25 to RJ-45 cable included with the IQ80960RM/RN can be

used to connect the console port to any standard RS-232 port on the host syste m.

The UART on the IQ80960RM/RN platform is clocked with a 1.843 MHz clock, and may be

programmed to use this clock with its internal baud rate counte rs. The UART register addresses are

shown in Ta ble 3- 5; refer to the 16C550 device data book for a detailed description of the registers

and device operation. Note that some UART addresses refer to different registers depending on

whether a read or a write is being performed.

3.5 Secondary PCI Bus Expansion Connectors

Four PCI Expansion Slots are available on the IQ80960RM/RN platform. Th e IQ80960RM

supports 32-bit PCI expansion and the IQ80960RN supports 64-bit PCI expa nsion. The slots are

designed for +5V PCI signalling and accommodate PCI cards with +5V or universal sign alling

capabilities.

3.5.1 PCI Slots Power Availability

Power from the Primary PCI bus, +3.3V, +5V, +12V, and –12V, is routed to the Secondary PCI bus

expansion slots. +3.3V is only available at the secondary PCI slots if the host system makes +3.3V

available on the Primary PCI slots. LED CR5 indicates if thi s power is available.

Table 3-5. UART Register Addresses

Address Read Regi ster Write Register

E000 0000H Receive Holding R egister Transmit Holding R egister

E000 0001H Unused Interrupt Enable Register

E000 0002H Interrupt Status R egister FIFO Control Regist er

E000 0003H Unused Line Control Register

E000 0014H Unused Modem Control Register

E000 0015H Line Status Regist er Unused

E000 0016H Modem Status Register Unused

E000 0017H Scratchpad Register Scratchpad Register

Contents

Main IQ80960RM/RN Evaluation Platform Board Manual Contents Page Figures Tables Page Introduction Figure 1-2. IQ80960RN Platform Physical Diagram 1.1 i960 RM/RN I/O Processor and IQ80960RM/RN Features 1.2 Software Development Tools 1.3 Tornado* for I20* Software Development Toolset 1.3.1 IxWorks* Real-Time Operating System 1.3.2 TORNADO Build Tools 1.3.3 TORNADO Test and Debug Tools 1.4 CTOOLS Software Development Toolset 1.4.1 CTOOLS and the MON960 Debug Monitor 1.4.1.1 MON960 Host Communications 1.4.1.2 Terminal Emulation Method 1.4.1.3 Host Debugger Interface (HDI) Method 1.6 About This Ma nu a l A brief description of the contents of this manual follows. 1.7 Notational-Conventions 1.8 Technical Support 1.8.1 Intel Customer Electronic Mail Support 1.8.2 Intel Custom er Supp or t Con tacts Evaluation Board Manual 1-9 1.8.3 Related Information RM/RN I/O Processor Design Guide i Contact Cyclone Microsystems for additional inf orma tion about their products and literature: Table 1-1. Document Information Page Getting Started 2.1 Pre-Installation Considerations 2.2 Software Installation 2.2.1 Installing Software Development Tools Getting Started 2.3 Hardware Installation 2.3.1 Battery Backup 2.3.2 Installing the IQ80960RM/RN Platforms in the Host System 2.3.3 Verify IQ80960RM/RN Platform is Functional Getting Started 2.4 Creating and Downloading Executable Files 2.4.1 Sample Download and Execution Using GDB960 Page Hardware Reference 3.1 Power Requirements 3.2 SDRAM 3.2.1 SDRAM Performance 3.2.2 Upgrading SDRAM 3.3 Flash ROM 3.3.1 Flash ROM Programming 3.4 Console Serial Port 3.5 Secondary PCI Bus Expansion Connectors 3.5.1 PCI Slots Power Availability 3.5.2 Interrupt and IDSEL Routing 3.6 Battery Backup 3.7 Loss of Fan Detect 3-6 IQ80960RM/RN 3.8 Logic Analyzer Headers 3.9 JTAG Header 3.10 User LEDs 3.10.1 User LEDs During Initialization Evaluation Board Manual 3-9 Tabl e 3-11 lists the connectors and LEDs. Table 3-11. IQ80960RM/RN Connectors and LEDs Page i960 Evaluation Board Manual 4-1 RM/RN I/O Processor Overview 4-2 IQ80960RM/RN 4.1 CPU Memory Map 4.2 Local Interrupts 4-4 IQ80960RM/RN Figure 4-3. i960 RM /RN I/O Processor Interrup t Controller Con nection s i960RN/RM I/O Processor 4.3 CPU Counter/Timers 4.4 Primary PCI Interface 4.5 Secondary PCI Interface 4.6 DMA Channels 4.7 Application Accelerator Unit 4.8 Performance Monitor Unit Page MON960 Support for IQ80960RM/RN 5.1 Secondary PCI Bus Expansion Connectors 5.2 MON960 Components 5.2.1 MON960 Initializatio n Initialization firmware MON960 extensions MON960 kernel Diagnostics/example code 5.2.2 80960JT Core Initialization 5.2.3 Memory Controller Initialization 5.2.4 SDRAM Initialization 5.2.5 Primary PCI Interface Initialization 5.2.6 Primary ATU Initialization 5.2.7 PCI-to-PCI Bridge Initialization 5.2.8 Secondary ATU Initialization 5.3 MON960 Kernel 5.4 MON960 Extensions 5.4.1 Secondary PCI Initialization 5.4.2 PCI BIOS Routines 5.4.2.1 sysPCIBIOSPresent 5.4.2.2 sysFindPCIDevice 5.4.2.3 sysFindPCIClassCode 5.4.2.4 sysGenerateSpecialCycle 5.4.2.5 sysReadConfigByte 5.4.2.6 sysReadConfigWord 5.4.2.7 sysReadConfigDword 5.4.2.8 sysWriteConfigByte 5.4.2.9 sysWriteConfigWord 5.4.2.10 sysWriteConfigDword 5.4.2.11 sysGetIrqRoutingOptions 5.4.2.12 sysSetPCIIrq 5.4.3 Additional MON960 Commands 5.4.3.1 print_pci Utility 5.5 Diagnostics / Example Code 5.5.1 Board Level Diagnostics 5.5.2 Secondary PCI Diagnostics Evaluation Board Manual A-1 Bill of Materials A Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4) A-2 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4) Evaluation Board Manual A-3 Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4) A-4 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4) Evaluation Board Manual A-5 Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 5) A-6 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 5) Evaluation Board Manual A-7 Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 5) A-8 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 5) Page Page Evaluation Board Manual B-1 Schematics B SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 Page SPARES Evaluation Board Manual B-13 Schematics Table B-2. IQ80960RM Schematics List SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 SPARES Page PLD Code C Page Recycling the Battery D