5-4 IQ80960RM/RN
Evaluation Board Manual
MON960 Support for IQ80960RM/RN
By default, Primary Outbound Configuration Cycle parameters are not established. The AT U
Configuration Register (ATUCR) is initialized to establish the operational parameters for the
Doorbell Unit and ATU interrupts (both primary and secondary), and to enable the primary and
secondary ATUs. The PCI host is respon sible for allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the PCI Base addresses for the IQ80960RM/RN platform.
5.2.7 PCI-to-PCI Bridge Initialization
PCI-to-PCI Bridge initialization includes in itialization by the 80960JT core and initiali zation by the
PCI host processor. Local initialization occurs first and consists mainly of es tablishing the operational
parameters for the secondary PCI interface of t he PCI-to-PCI bridge. On the IQ80960R M/RN
platform, the secondary PC I bus is configured to consist of pr ivate devices (not visible to PCI host
configuration cycles). To support a private secondary PCI bus, the Secondary IDSEL Select Register
(SISR) is initialized to prevent the secondary PCI address bits [20:16] from being asserted d uring
conversion of PCI Type 1 configuration c ycles on the primary PCI bus to PCI Type 0 configuration
cycles on the secondary PCI bus. Secondary PCI bus masters are prevented from initiating
transactions that will be forwarded to the prim ary PCI interface. The PCI host is responsible for
assigning and initializing the PCI bus numbers , allocating PCI address space (Memory, Memory
Mapped I/O, and I/O), and assigning the IRQ nu mbers to valid interrupt routing values.
5.2.8 Secondary ATU Initialization
Secondary ATU (Bridge) initialization consists mainly of establishi ng the operational parameters
for access between the local IQ80960RM/RN platform bus and the secondary PCI devices. The
Secondary Inbound ATU Base Address Register (SIABAR) is initialized to establish the PCI base
address of IQ80960RM/RN platform local memory from the secondary PCI bus. By convention,
the secondary PCI base address for access to IQ80960RM/RN platform local memory is “0”. The
Secondary Inbound ATU Limit Register (SIALR) is initialized to establish the bloc k si ze of
memory required by the secondary AT U. The SIALR value is based on the installed SDRAM
configuration. The Secondary Inbound ATU Translate V alue Register (SIATVR) is initialized to
establish the translation value for Secondary PCI-t o-Local accesses. The SIATVR value is set to
reference the base of local SDRAM. The Secondary Outbound Memory Window Value Register
(SOMWVR) is initialized to establis h the translation value for Local-to-Secondary PCI accesses.
The SOMWVR value is left at its default value of “0” to allow the IQ80960RM/RN platform to
access the start of the PCI Memory address map. Likewise, the Secondary Outbound I/O Window
Value Register (SOIOWVR) is le f t at its d e fa ult value of “0” to allow th e IQ 8 0 960 RM/RN
platform to access the start of the PCI I/O address map.
On the secondary PCI bus, the IQ80960RM/RN platform assumes the duties of PCI host and, as
such, is required to configure the devices of the secondary PCI bus. Secondary Outbound
Configuration Cycle parameters are established duri ng s econdary PCI bus configuration.
Secondary PCI bus configuration is accomplished via MON960 Extension routines.