Intel IQ80960RM, RN Introduction

IQ80960RM/RN

Evaluation Board Manual 1-1

Introduction

1

This manual describes the IQ80960RM and IQ80960RN evaluation platforms for Intel’s i960®

RM/RN I/O processor. The i960 RM/RN I/O processors combine an 80960JT core with two PCI

bus interfaces, as w ell as a memory cont roller, DMA channels , an interrupt contr oller interface, and

an I2C serial bus. The difference between the two processors is that the 80960RN utilizes 64-bit

primary PCI and secondary PCI buses while the 80960RM utilizes both a 32-bit primary and

secondary PCI bus. The IQ80960RM and IQ80960RN platforms are ful l-leng th PCI adapter boa rds

and are 8.9” in height to accommodate four standard PCI connectors on the secondary PCI bus.

The boards can be installed in any PCI host system that complies with the PCI Local Bus

Specification Revision2.1. PCI devices can be connected to the secondary bus to build powerful

intelligent I/O subsystems.

Figure 1-1. IQ80960RM/IQ80960RN Platform Functional Block Diagram

i960® RM/RN

I/O Processor

Flash

ROM

Logic

Analyzer

Interface

LED

Register

UART

Logic Analyzer Interface

Battery

Backup

Support

Primary PCI Bus 32/64-bits

SDRAM (x72)

Secondary PCI Sl ot 1

Secondary PCI Sl ot 2

Secondary PCI Slot 3

Secondary PCI Sl ot 4

Secondary PCI

Bus 32/64-bits

ROM Bus

User

LED

RS-232

Serial Port

Console

Port

Contents

Main IQ80960RM/RN Evaluation Platform Board Manual Contents Page Figures Tables Page Introduction Figure 1-2. IQ80960RN Platform Physical Diagram 1.1 i960 RM/RN I/O Processor and IQ80960RM/RN Features 1.2 Software Development Tools 1.3 Tornado* for I20* Software Development Toolset 1.3.1 IxWorks* Real-Time Operating System 1.3.2 TORNADO Build Tools 1.3.3 TORNADO Test and Debug Tools 1.4 CTOOLS Software Development Toolset 1.4.1 CTOOLS and the MON960 Debug Monitor 1.4.1.1 MON960 Host Communications 1.4.1.2 Terminal Emulation Method 1.4.1.3 Host Debugger Interface (HDI) Method 1.6 About This Ma nu a l A brief description of the contents of this manual follows. 1.7 Notational-Conventions 1.8 Technical Support 1.8.1 Intel Customer Electronic Mail Support 1.8.2 Intel Custom er Supp or t Con tacts Evaluation Board Manual 1-9 1.8.3 Related Information RM/RN I/O Processor Design Guide i Contact Cyclone Microsystems for additional inf orma tion about their products and literature: Table 1-1. Document Information Page Getting Started 2.1 Pre-Installation Considerations 2.2 Software Installation 2.2.1 Installing Software Development Tools Getting Started 2.3 Hardware Installation 2.3.1 Battery Backup 2.3.2 Installing the IQ80960RM/RN Platforms in the Host System 2.3.3 Verify IQ80960RM/RN Platform is Functional Getting Started 2.4 Creating and Downloading Executable Files 2.4.1 Sample Download and Execution Using GDB960 Page Hardware Reference 3.1 Power Requirements 3.2 SDRAM 3.2.1 SDRAM Performance 3.2.2 Upgrading SDRAM 3.3 Flash ROM 3.3.1 Flash ROM Programming 3.4 Console Serial Port 3.5 Secondary PCI Bus Expansion Connectors 3.5.1 PCI Slots Power Availability 3.5.2 Interrupt and IDSEL Routing 3.6 Battery Backup 3.7 Loss of Fan Detect 3-6 IQ80960RM/RN 3.8 Logic Analyzer Headers 3.9 JTAG Header 3.10 User LEDs 3.10.1 User LEDs During Initialization Evaluation Board Manual 3-9 Tabl e 3-11 lists the connectors and LEDs. Table 3-11. IQ80960RM/RN Connectors and LEDs Page i960 Evaluation Board Manual 4-1 RM/RN I/O Processor Overview 4-2 IQ80960RM/RN 4.1 CPU Memory Map 4.2 Local Interrupts 4-4 IQ80960RM/RN Figure 4-3. i960 RM /RN I/O Processor Interrup t Controller Con nection s i960RN/RM I/O Processor 4.3 CPU Counter/Timers 4.4 Primary PCI Interface 4.5 Secondary PCI Interface 4.6 DMA Channels 4.7 Application Accelerator Unit 4.8 Performance Monitor Unit Page MON960 Support for IQ80960RM/RN 5.1 Secondary PCI Bus Expansion Connectors 5.2 MON960 Components 5.2.1 MON960 Initializatio n Initialization firmware MON960 extensions MON960 kernel Diagnostics/example code 5.2.2 80960JT Core Initialization 5.2.3 Memory Controller Initialization 5.2.4 SDRAM Initialization 5.2.5 Primary PCI Interface Initialization 5.2.6 Primary ATU Initialization 5.2.7 PCI-to-PCI Bridge Initialization 5.2.8 Secondary ATU Initialization 5.3 MON960 Kernel 5.4 MON960 Extensions 5.4.1 Secondary PCI Initialization 5.4.2 PCI BIOS Routines 5.4.2.1 sysPCIBIOSPresent 5.4.2.2 sysFindPCIDevice 5.4.2.3 sysFindPCIClassCode 5.4.2.4 sysGenerateSpecialCycle 5.4.2.5 sysReadConfigByte 5.4.2.6 sysReadConfigWord 5.4.2.7 sysReadConfigDword 5.4.2.8 sysWriteConfigByte 5.4.2.9 sysWriteConfigWord 5.4.2.10 sysWriteConfigDword 5.4.2.11 sysGetIrqRoutingOptions 5.4.2.12 sysSetPCIIrq 5.4.3 Additional MON960 Commands 5.4.3.1 print_pci Utility 5.5 Diagnostics / Example Code 5.5.1 Board Level Diagnostics 5.5.2 Secondary PCI Diagnostics Evaluation Board Manual A-1 Bill of Materials A Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4) A-2 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4) Evaluation Board Manual A-3 Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4) A-4 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4) Evaluation Board Manual A-5 Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 5) A-6 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 5) Evaluation Board Manual A-7 Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 5) A-8 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 5) Page Page Evaluation Board Manual B-1 Schematics B SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 Page SPARES Evaluation Board Manual B-13 Schematics Table B-2. IQ80960RM Schematics List SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 SPARES Page PLD Code C Page Recycling the Battery D