Intel IQ80960RM, RN 4.8 Performance Monitor Unit

IQ80960RM/RN

Evaluation Board Manual 4-7

i960® RM/RN I/O Processor Overview

Figure 4-5 shows a simplified connection of the Application Accelera tor to the i960 RM/RN I/O

Processor Internal Bus.

4.8 Performance Monitor Unit

The Performance Monitoring features aid in measuring and monitoring various system parameters

that contribute to the overall performance of the process or. The monitoring facility is genericall y

referred to as PMON – Performance Monitoring. The facility is model specific, not architectural;

its intended use is to gather p erformance measurements that can be used to retune/ref ine code for

better system level performance.

The PMON facility provided on the i960 RM/RN I/O processor comprises:

•One dedicated global Time Stamp counter, and

•Fourteen (14) Programmable Event counters

The global time stamp counter is a dedicated, free running 32-bit counter.

The programmable even t cou n t er s ar e 3 2-b i ts w i de . Ea ch counter can be program m e d to ob se rve

an event from a defined set of events. An event consists of a set of parameters which define a start

condition and a stop condition. The monitored eve nts are selected by programming an event select

register (ESR).

Figure 4-5. Application Accelerator Unit

64-bit

Data Queue

Application Accelerator Uni t

Packing/

Unpacking

Unit

80960

Bus Interface Internal Bus

Boolean Unit

Contents

Main IQ80960RM/RN Evaluation Platform Board Manual Contents Page Figures Tables Page Introduction Figure 1-2. IQ80960RN Platform Physical Diagram 1.1 i960 RM/RN I/O Processor and IQ80960RM/RN Features 1.2 Software Development Tools 1.3 Tornado* for I20* Software Development Toolset 1.3.1 IxWorks* Real-Time Operating System 1.3.2 TORNADO Build Tools 1.3.3 TORNADO Test and Debug Tools 1.4 CTOOLS Software Development Toolset 1.4.1 CTOOLS and the MON960 Debug Monitor 1.4.1.1 MON960 Host Communications 1.4.1.2 Terminal Emulation Method 1.4.1.3 Host Debugger Interface (HDI) Method 1.6 About This Ma nu a l A brief description of the contents of this manual follows. 1.7 Notational-Conventions 1.8 Technical Support 1.8.1 Intel Customer Electronic Mail Support 1.8.2 Intel Custom er Supp or t Con tacts Evaluation Board Manual 1-9 1.8.3 Related Information RM/RN I/O Processor Design Guide i Contact Cyclone Microsystems for additional inf orma tion about their products and literature: Table 1-1. Document Information Page Getting Started 2.1 Pre-Installation Considerations 2.2 Software Installation 2.2.1 Installing Software Development Tools Getting Started 2.3 Hardware Installation 2.3.1 Battery Backup 2.3.2 Installing the IQ80960RM/RN Platforms in the Host System 2.3.3 Verify IQ80960RM/RN Platform is Functional Getting Started 2.4 Creating and Downloading Executable Files 2.4.1 Sample Download and Execution Using GDB960 Page Hardware Reference 3.1 Power Requirements 3.2 SDRAM 3.2.1 SDRAM Performance 3.2.2 Upgrading SDRAM 3.3 Flash ROM 3.3.1 Flash ROM Programming 3.4 Console Serial Port 3.5 Secondary PCI Bus Expansion Connectors 3.5.1 PCI Slots Power Availability 3.5.2 Interrupt and IDSEL Routing 3.6 Battery Backup 3.7 Loss of Fan Detect 3-6 IQ80960RM/RN 3.8 Logic Analyzer Headers 3.9 JTAG Header 3.10 User LEDs 3.10.1 User LEDs During Initialization Evaluation Board Manual 3-9 Tabl e 3-11 lists the connectors and LEDs. Table 3-11. IQ80960RM/RN Connectors and LEDs Page i960 Evaluation Board Manual 4-1 RM/RN I/O Processor Overview 4-2 IQ80960RM/RN 4.1 CPU Memory Map 4.2 Local Interrupts 4-4 IQ80960RM/RN Figure 4-3. i960 RM /RN I/O Processor Interrup t Controller Con nection s i960RN/RM I/O Processor 4.3 CPU Counter/Timers 4.4 Primary PCI Interface 4.5 Secondary PCI Interface 4.6 DMA Channels 4.7 Application Accelerator Unit 4.8 Performance Monitor Unit Page MON960 Support for IQ80960RM/RN 5.1 Secondary PCI Bus Expansion Connectors 5.2 MON960 Components 5.2.1 MON960 Initializatio n Initialization firmware MON960 extensions MON960 kernel Diagnostics/example code 5.2.2 80960JT Core Initialization 5.2.3 Memory Controller Initialization 5.2.4 SDRAM Initialization 5.2.5 Primary PCI Interface Initialization 5.2.6 Primary ATU Initialization 5.2.7 PCI-to-PCI Bridge Initialization 5.2.8 Secondary ATU Initialization 5.3 MON960 Kernel 5.4 MON960 Extensions 5.4.1 Secondary PCI Initialization 5.4.2 PCI BIOS Routines 5.4.2.1 sysPCIBIOSPresent 5.4.2.2 sysFindPCIDevice 5.4.2.3 sysFindPCIClassCode 5.4.2.4 sysGenerateSpecialCycle 5.4.2.5 sysReadConfigByte 5.4.2.6 sysReadConfigWord 5.4.2.7 sysReadConfigDword 5.4.2.8 sysWriteConfigByte 5.4.2.9 sysWriteConfigWord 5.4.2.10 sysWriteConfigDword 5.4.2.11 sysGetIrqRoutingOptions 5.4.2.12 sysSetPCIIrq 5.4.3 Additional MON960 Commands 5.4.3.1 print_pci Utility 5.5 Diagnostics / Example Code 5.5.1 Board Level Diagnostics 5.5.2 Secondary PCI Diagnostics Evaluation Board Manual A-1 Bill of Materials A Table A-1. IQ80960RN Bill of Materials (Sheet 1 of 4) A-2 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 2 of 4) Evaluation Board Manual A-3 Table A-1. IQ80960RN Bill of Materials (Sheet 3 of 4) A-4 IQ80960RM/RN Table A-1. IQ80960RN Bill of Materials (Sheet 4 of 4) Evaluation Board Manual A-5 Table A-2. IQ80960RM Bill of Materials (Sheet 1 of 5) A-6 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 2 of 5) Evaluation Board Manual A-7 Table A-2. IQ80960RM Bill of Materials (Sheet 3 of 5) A-8 IQ80960RM/RN Table A-2. IQ80960RM Bill of Materials (Sheet 4 of 5) Page Page Evaluation Board Manual B-1 Schematics B SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 Page SPARES Evaluation Board Manual B-13 Schematics Table B-2. IQ80960RM Schematics List SDRAM DECOUPLING SPCI DECOUPLING IC DECOUPLING Page Page SPARES Page Page Page SPCI CONN 2 SPCI CONN 1 SPCI CONN 4 SPCI CONN 3 SPARES Page PLD Code C Page Recycling the Battery D