i960® RM/RN I/O Processor Overview

4.3CPU Counter/Timers

The i960 RM/RN I/O processor is equipped with two on-chip counter/timers which are clocked with the i960 RM/RN I/O processor clock signal. The i960 RM/RN I/O processor receives its clock from the primary PCI interface clock, generated by the motherboard. Most motherboards generate a 33 MHz clock signal, although the PCI specification requires a clock frequency between 0 and 33 MHz. The timers can be programmed for single-shot or continuous mode, and can generate interrupts to the processor when the countdown expires.

4.4Primary PCI Interface

The primary PCI interface on the IQ80960RM/RN platform provides the i960 RM/RN I/O processor with a connection to the PCI bus on the host system. Only the PCI-to-PCI bridge unit on the i960 RM/RN I/O processor is directly connected to the primary PCI interface. Devices installed on the expansion slots are connected to the PCI bus via the bridge unit on the i960 RM/RN I/O processor. The PCI-to-PCI bridge accepts Type 1 configuration cycles destined for devices on the secondary bus, and will forward them as Type 0 or Type 1 configuration cycles, or as special cycles. The IQ80960RN platform interfaces to a 64-bit PCI bus and the IQ80960RM platform interfaces to a 32-bit PCI bus.

4.5Secondary PCI Interface

The secondary PCI interface provided by the i960 RM/RN I/O processor is used to connect PCI cards via the expansion slots to the host system’s PCI bus. PCI cards are attached to the IQ80960RM/RN platform with a standard PCI connector and may contain up to four separate PCI devices. The i960 RM/RN I/O processor provides PCI-to-PCI bridge functionality to map installed PCI devices onto the host PCI bus, and supports transaction forwarding in both directions across the bridge. PCI devices connected via the expansion slots can therefore act as masters or slaves on the host system’s PCI bus. Additional PCI-to-PCI bridge devices are supported by the i960 RM/RN I/O processor on its secondary PCI interface and can be designed into add-on PCI cards. In addition, the i960 RM/RN I/O processor supports “private” PCI devices on its secondary bus. Private devices are hidden from initialization code on the host system, and are configured and accessed directly by the i960 RM/RN I/O processor. These devices are not part of the normal PCI address space, but they can act as PCI bus masters and transfer data to and from other PCI devices in the system.

Unless designated as private devices, PCI devices installed on the secondary PCI interface of the IQ80960RM/RN platform are mapped into the system-wide PCI address space by configuration software running on the host system. No logical distinction is made at the system level between devices on the primary PCI bus and devices on secondary buses; all transaction forwarding is handled transparently by the PCI-to-PCI bridge. Configuration cycles and read and write accesses from the host are forwarded through the PCI-to-PCI bridge unit of the i960 RM/RN I/O processor. Master read and write cycles from devices on the secondary PCI bus are also forwarded to the host bus by the PCI-to-PCI bridge unit.

IxWORKS allows secondary PCI devices to be configured as Public or Private. Public devices are configured by the PCI host. Private devices are configured by the IxWORKS kernel and the device-specific HDM.

IQ80960RM/RN Evaluation Board Manual

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Intel IQ80960RM, RN manual CPU Counter/Timers, Primary PCI Interface, Secondary PCI Interface
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RN, IQ80960RM specifications

The Intel IQ80960RM and RN are part of the Intel i960 family of microprocessors, which were specifically designed for embedded applications in real-time computing environments. Introduced in the early 1990s, these processors were aimed at providing high-performance processing capabilities in industrial, telecommunications, and military systems.

One of the key features of the IQ80960RM and RN is their ability to support a 32-bit architecture, delivering a significant performance advantage over 16-bit and earlier processors. This architecture enables the execution of complex algorithms and the management of large amounts of data, making these microprocessors suitable for demanding applications.

The i960 family is built around a superscalar architecture, allowing multiple instructions to be completed in a single clock cycle. This is achieved through advanced instruction pipelining, which significantly boosts throughput and overall computational speed. The IQ80960RM and RN also included features like branch prediction and out-of-order execution, enhancing efficiency and reducing latency in real-time applications.

Memory management capabilities are another strong point of the IQ80960RM and RN. They support both virtual and physical memory addressing, enabling sophisticated memory management strategies. Their integrated memory management unit (MMU) allows for easier and more effective memory allocation, critical for real-time operating systems that require precise timing and resource management.

Furthermore, these processors are designed with an extensive instruction set architecture (ISA), which supports a wide range of operations, including digital signal processing (DSP) tasks. This versatility allows them to be utilized in various applications, from automotive systems to robotics, where reliable performance is paramount.

The thermal performance and power efficiency of the IQ80960RM and RN has also been a notable characteristic. With operational capabilities across various temperature ranges, these chips are well-suited for harsh environments often found in industrial settings.

In terms of connectivity, the IQ80960 series supports multiple I/O interfaces and communication protocols, ensuring that they can integrate seamlessly with other components and systems. This flexibility enhances their usability in networked applications, particularly in embedded systems.

Overall, the Intel IQ80960RM and RN processors represent a significant step forward in embedded processor technology, characterized by their robust performance, advanced features, and ability to meet the stringent demands of real-time applications across various industries.
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