AT INTERFACE DESCRIPTION
5 – 5

Ultra DMA TimingUltra DMA Timing

Ultra DMA TimingUltra DMA Timing

Ultra DMA Timing

TIMING PARAMETERS
(all times in nanoseconds)
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tCYC C
y
cle Time (from STROBE ed
g
e to STROBE ed
g
e) 112 73 54 39 25 16.8
t2CYC Two c
y
cle time (from r is in
g
ed
g
e to next risin
g
ed
g
e or
from fallin
g
ed
g
e to next fallin
g
ed
g
e of STROBE) 230 153 115 86 57 38
tDS Data setup time (at recipient) 15 10 7 7 5 4
tDH Data hold time (at recipient) 5 5 5 5 5 4.6
tDVS Data valid setup time at sender (time from data bus bein
g
valid unti l S TROBE ed
g
e) 70 48 31 20 6.7 4.8
tDVH Data valid hold time at sender (time from STROBE ed
g
e
until data ma
y
g
o invalid) 6.2 6.2 6.2 6.2 6.2 4.8
tFS First S TROBE (ti m e for de vice to se nd first STROBE) 0 230 0 2 00 0 170 0 1 30 0 120 0 90
tLI Limited interlock time (time allowed between an action b
y
one a
g
ent, either host or device, and the followin
g
action
b
y
the other a
g
ent) 0 150 0 150 0 150 0 100 0 100 0 75
tMLI Interlock ti me with minimum 20 20 20 20 20 20
tUI Unlimited interlock time 000000
tAZ Maximum time allowed for outputs to release 10 10 10 10 10 10
tZAH Minimum dela
y
time required for output drivers turnin
g
on
(from released state )
20 20 20 20 20 20
tZAD 000000
tENV Envelope time (all contro l si
g
nal transitions are within the
DMACK envelope b
y
this much time) 20 70 20 70 20 70 20 55 20 55 20 50
tSR STROBE to DMARDY (response time to ensure the
s
y
nchronous pause case when the recipient is pausin
g
)50 30 20 NA NA NA
tRFS Read
y
-to-final-STROBE time (no more STROBE ed
es
ma
y
be sent this lon
g
after receivin
g
DMARDY- ne
g
ation) 75 70 60 60 60 50
tRP Read
y
-to-pause time (time until a recipient ma
y
assume
that the sender has paused after ne
g
ation of DMARDY-) 160 125 100 100 100 85
tIORDYZ Pull-up time before allowin
g
IORDY to be releas ed 20 20 20 20 20 20
tZIORDY Minimum time device shall wait before drivin
g
IORDY000000
tACK Setup and hold times before assertion and ne
g
ation of
DMACK- 20 20 20 20 20 20
tSS Time from STROBE ed
g
e to STOP assertion when the
sender is stoppin
g
50 50 50 50 50 50
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
tZAD
DA0, DA1, DA2,
CS0-, CS1-
tUI
tZAD
tACK
tACK
tENV
tENV
tZIORDY
tFS
tFS
tVDS
tAZ tDVH
tACK

Figure 5 - 4

Initiating an Ultra DMA Data In Burst