Reset and Interrupt Handling | Maxtor 2B010H1, 2B015H1, 2B020H1

HOST SOFTWARE INTERFACE

Reset and Interrupt Handling

Reset Handling

One of three different conditions may cause a reset: power on, hardware reset or software reset. All three cause the interface processor to initialize itself and the Task File registers of the interface. A reset also causes a set of the Busy bit in the Status register. The Busy bit does not clear until the reset clears and the drive completes initialization. Completion of a reset operation does not generate a host interrupt.

Task File registers are initialized as follows:

Error		1
Sector	Count	1
Sector	Number	1
Cylinder Low		0
Cylinder High		0
Drive/Head		0

Interrupt Handling

The drive requests data transfers to and from the host by asserting its IRQ 14 signal. This signal interrupts the host if enabled by bit 1 (IRQ enable) of the Fixed Disk Control register.

Clear this interrupt by reading the Status register, writing the Command register, or by executing a host hardware or software reset.

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Maxtor 2B010H1, 2B015H1, 2B020H1 manual Reset and Interrupt Handling

Contents

Maxtor 541DX Product Manual Before You Begin U T I O N Contents Product Specifications Handling and Installation AT Interface Description Interface CommandsHost Software Interface Service and Support Glossary Figures Introduction MaxtorCorporationManualOrganization Abbreviations Conventions Key Features ProductDescription Functional / Interface Product FeaturesModels CYL SP T MAX LBA Capacity CacheManagement Major HDA Components SubsystemConfiguration Jumper Location / ConfigurationJumper Configuration Cylinder Limitation Jumper Description ProductSpecifications Drive ConfigurationPerformanceSpecifications Models and Capacities Physical Dimensions Param Eter Valu E PowerRequirements Power Mode DefinitionsEPA Energy Star Compliance Environmental Limits Shock and Vibration Reliability SpecificationsParam Eter Oper AT ING ON- Oper AT ING Safety Regulatory Compliance EMC/EMI Hard Drive Handling Precautions HandlingandInstallationElectro-Static Discharge ESD Unpacking and Inspection Multi-pack Shipping Container Physical Installation Repacking Before You Begin Hook up Set up Start up InterfaceConnector ATInterfaceDescriptionPinDescriptionSummary PIN IGN AL PIN Name Signal Name Signal Desc Ription Pin Description Table IM in G Paramet ERS Mode PIO Timing Imin G Paramet ERS Mode DMATiming Ultra DMA Timing Mode Sustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Task File Registers HostSoftwareInterfacePOR T EAD WR ITE Conten TS LBA Bits CommandRegister Seek, Format, and Diagnostic Commands Summary M M a N D N a M E M M a N D code PA R a M E T E R S U S E D Control Diagnostic Registers Reset and Interrupt Handling InterfaceCommands ReadCommands Read DMA WriteCommands Write Multiple VAL UE DES C RIP Tion ModeSet/CheckCommandsEC TOR LE VE L VAL UE Omman D PowerModeCommands Timer VAL UE TIME-OUT Period Sleep Mode InitializationCommands Or D ENT Desc Ription Or D 15- 10, as c urrently defined Initialize Drive Parameters Seek,FormatandDiagnosticCommands ER ROR Code Desc Ription A.R.T. CommandSet Key Register ServiceandSupport Service PolicyNo Quibble Service Product Support From Dial Glossary Correctable error Central processing unit CPUChannel Character Direct access Direct memory access DMAError correction code ECC Error free Hard error Head disk assembly HDAFrequency response Gigabyte GB Late window LatencyLogic Logical address Phase locked loop PLL Phase marginRandom access memory RAM Read gate signal Sector pulse signal Seek complete signalSequential access Soft error Strobe offset signal Un-correctable errorUnrecoverable error Write gate signal