340 Chapter 6. Function Reference
Description
Time domain simulation of a sampled data interconnection. The applicable closed loop
system is illustrated below.
SysdSys
-
vw
y
u
This is conceptually the equivalent of:
v=starp(Sys,dSys)∗w.
This function will handle interconnections in which the continuous time signals are not
necessarily synchronized with the digital system. Computation delays which are a
fraction of the sample period may also be simulated. The following equations represent
the discrete system,
z(kT +T)=A
d
z(kT)+B
d
y(kT)
u(kT +cdelay)=C
d
z(kT)+D
d
y(kT)
Fordelays of greater than a sample per iod append additional states to dSys to model the
integer sample period part of the delay. Use cdelay to model the fractional remainder.
The actual calculation is performed with a fast discrete time equivalent. Intstep is the
fast integration step size. The input vector, wwill be interpolated to the samestep size.
Either a zero or first order interpolation is used, depending on the keyword ord. If ord =
0 a zero-order hold equivalentis used for the continuous plant. In the ord = 1 case a