©
National Instruments Corporation I-1 DIO 6533 User Ma nual

Index

Numbers
+5 V signal
connecting to GND, RGND, or output pin
(caution), 4-14
description (table), 4-5
8255 emulation, 5-4 to 5-7
input, 5-5 to 5-6
output, 5-6 to 5-7
purpose and use, 3-9
timing specifications (figure), 5-8
A
ACK<1..2> signal. See also level ACK mode.
control signal summary (table), 4-7
description (table), 4-3
reversing pin assignments (note), 4-2
timing connections, 4-13
adapter, optional
description, B-1
pin assignments (figure), B-2
addresses
base I/O address selection, 2-6
PC AT I/O address map (table), 2-6 to 2-8
AT device configuration, 2-5 to 2-9
base I/O address selection, 2-6
DMA channel selection, 2-6
interrupt channel selection, 2-6 to 2-9
Plug and Play mode, 2-5
switchless data acquisition, 2-5
AT-DIO-32HS
block diagram, 3-3
installation, 2-3
overview, 1-1
B
base I/O address selection, 2-6
bulletin board support, C-1
burst mode, 5-27 to 5-33
purpose and use, 3-10, 5-27 to 5-28
timing specifications, 5-28 to 5-33
input mode transfer example (figure),
5-28
input timing
default (figure), 5-31
PCLK reversed (figure), 5-33
output mode transfer example (figure),
5-29
output timing
default (figure), 5-30
PCLK reversed (figure), 5-32
bus interface specifications, A-8
C
change detection
definition, 3-6
purpose and use, 3-7 to 3-8
clocks, board and RTSI, 4-8
configuration
AT devices, 2-5 to 2-9
base I/O address selection, 2-6
DMA channel selection, 2-6