Chapter 5 Signal Timing
DIO 6533 User Manual 5-8 © National Instruments Corporation
8255 Emulation Mode Timing SpecificationsFigure 5-7 shows the timing diagram for 8255 emulation mode.
Figure 5-7. 8255 Emulation Timing
Parameter Description Minimum Maximum
Input Parameters
tr*r REQ low duration 75 —
trr* REQ high duration 75 —
ta*r ACK falling edge to REQ rising edge 0—
t
dir Input data valid to REQ rising edge 0—
t
rdi REQ rising edge to input data invalid 10 —
Output Parameters
taa* ACK high duration 100 —
tr*a REQ falling edge to ACK rising edge — 150
tdoa* Output data valid to ACK falling edge 25 —
trdo REQ rising edge to output data invalid 100 —
All timing values are in nanoseconds.
REQ
ACK
Data Out
Data In
tdoa*
tdir
ta*r
tr*r trr*
trdi
trdo
taa*
tr*a