National Instruments DIO 6533 H, I, L

©

National Instruments Corporation I-3 DIO 6533 User Ma nual

H

handshake timing, 5-4 to 5-33

8255 emulation, 5-4 to 5-7

burst mode, 5-27 to 5-33

leading-edge mode, 5-14 to 5-18

level-ACK mode, 5-9 to 5-14

long-pulse mode, 5-19 to 5-22

trailing-edge mode, 5-23 to 5-27

handshaking protocols, 3-8 to 3-10

8255 emulation, 3-9

burst mode, 3-10

comparison of protocols, 3-10 to 3-11

leading-edge pulse, 3-9

level ACK, 3-9

long pulse, 3-9

trailing-edge pulse, 3-9

handshaking transfer

controlling line polarities, 3-13

controlling startup sequence, 3-12

overview, 3-6

starting, 3-12 to 3-13

hardware configuration. See configuration.

hardware groups, 3-5

hardware installation. See installation.

hardware overview, 3-1 to 3-14

block diagrams

AT-DIO-32HS, 3-3

DAQCard-6533, 3-4

PCI-DIO-32HS/PXI-6533, 3-2

strobed I/O, 3-5 to 3-13

comparison of handshaking

protocols, 3-10 to 3-11

definition, 3-5

handshaking protocols, 3-8 to 3-10

pattern and change detection, 3-6 to

3-8

starting handshaking transfer, 3-12 to

3-13

transfer rates, 3-13 to 3-14

achieving highest possible rates, 3-13

to 3-14

maximum, 3-13

I

I/O connector, 4-1 to 4-9

control signal summary, 4-7

exceeding maximum ratings (note), 4-1

pin assignments (table), 4-2

RTSI bus interface, 4-7 to 4-9

signal characteristics, 4-6

signal descriptions (table), 4-3 to 4-5

initial state of signals, 4-6

installation

AT-DIO-32HS, 2-3

DAQCard-6533, 2-3 to 2-4

PCI-DIO-32HS, 2-1 to 2-2

PXI-6533, 2-2 to 2-3

software, 2-1

unpacking the DIO 6533, 1-8

interrupt channel selection, 2-6 to 2-9

PC AT 16-bit DMA channel assignment

map (table), 2-9

PC AT I/O address map (table), 2-6 to 2-8

PC AT interrupt assignment map (table),

2-8 to 2-9

L

leading-edge mode, 5-14 to 5-18

input, 5-14, 5-15

output, 5-14, 5-16

purpose and use, 3-9

timing specifications

input timing (figure), 5-17

output timing (figure), 5-18

level ACK mode, 5-9 to 5-13

input, 5-9, 5-10

output, 5-10 to 5-11

Contents

Main Page Important Information Warranty Copyright Trademarks WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS About This Manual Chapter 1 Introduction Chapter 2 Installation and Configuration Chapter 3 Hardware Overview Chapter 4 Signal Connections Chapter 5 Signal Timing Page Table About This Manual Organization of This Manual Conventions Used in This Manual National Instruments Documentation Related Documentation Customer Communication Introduction About the DIO 6533 Devices Using PXI with CompactPCI What You Need to Get Started Software Programming Choices National Instruments Application Software NI-DAQ Driver Software Register-Level Programming Optional Equipment Unpacking Installation and Configuration Software Installation Hardware Installation Installing the PCI-DIO-32HS Installing the PXI-6533 Installing the AT-DIO-32HS Installing the DAQCard-6533 PCI, PXI, and DAQCard Device Configuration AT Device Configuration Bus Interface Plug and Play Mode Switchless Data Acquisition Base I/O Address Selection DMA Channel Selection Interrupt Channel Selection National Instruments Corporation 2-7 DIO 6533 User Manual Table 2-1. PC AT I/O Address Map (Continued) Table 2-2 shows the PC AT interrupt assignments. DIO 6533 User Manual 2-8 National Instruments Corporation Table 2-2. PC AT Interrupt Assignment Map Table 2-1. PC AT I/O Address Map (Continued) National Instruments Corporation 2-9 DIO 6533 User Manual Table 2-3 shows the PC AT 16-bit DMA channel assignments. Note: EISA computers also have channels<0..3> available as 16-bit DMA channels. Table 2-3. PC AT 16-Bit DMA Channel Assignment Map Table 2-2. PC AT Interrupt Assignment Map (Continued) Hardware Overview Figure 3-1. PCI-DIO-32HS/PXI-6533 Block Diagram DIO 6533 User Manual 3-2 National Instruments Corporation Figure 3-2. AT-DIO-32HS Block Diagram National Instruments Corporation 3-3 DIO 6533 User Manual Unstrobed I/O Strobed I/OPattern Generation and Handshaking Pattern and Change Detection Pattern-Detection Triggers Change Detection Message Generation Handshaking Protocols 8255 Emulation Level ACK Leading-Edge Pulse Long Pulse Trailing-Edge Pulse Burst Mode Comparing Protocols Table 3-1. National Instruments Corporation 3-11 DIO 6533 User Manual 6533 Handshaking Protocols Starting a Handshaking Transfer Controlling the Startup Sequence Controlling Line Polarities Transfer Rates Page Signal Connections I/O Connector ! Chapter 4 Signal Connections DIO 6533 User Manual 4-2 National Instruments Corporation Figure 4-1. 6533 Device I/O Connector Pin Assignments Signal Descriptions Page Page Signal Characteristics Control Signal Summary RTSI Bus Interface Board and RTSI Clocks RTSI Triggers Data Signal Connections Unstrobed I/O Chapter 4 Signal Connections Figure 4-3. Example of Data Signal Connections National Instruments Corporation 4-11 DIO 6533 User Manual Strobed I/O Timing Connections Pull-Up and Pull-Down Connections Power Connections ! Field Wiring and Termination Page Page Signal Timing Pattern-Generation Timing Request Timing Internal Requests External Requests t t t t t Trigger Timing t t t t t t Handshake Timing 8255 Emulation Input Output Page 8255 Emulation Mode Timing Specifications t t t t t t t Other Asynchronous Modes Level-ACK Mode Page National Instruments Corporation 5-11 DIO 6533 User Manual Figure5-9 shows an output transfer in level-ACK mode. Figure 5-9. Level-ACK Mode Output Figures5-10 and5-11 show the timing diagrams for level-ACK mode. Level-ACK Mode Timing Specifications Page t t Leading-Edge Mode National Instruments Corporation 5-15 DIO 6533 User Manual Figure 5-12 shows an input transfer in leading-edge mode. Figure 5-12. Leading-Edge Mode Input DIO 6533 User Manual 5-16 National Instruments Corporation Figure5-13 shows an output transfer in leading-edge mode. Figure 5-13. Leading-Edge Mode Output Leading-Edge Mode Timing Specifications Figures5-14 and5-15 show the timing diagrams for leading-edge mode. Page t Long-Pulse Mode DIO 6533 User Manual 5-20 National Instruments Corporation Figure 5-17. Long-Pulse Mode Output Long-Pulse Mode Timing Specifications Figures5-18 and5-19 show the timing diagrams for long-pulse mode. Page t Trailing-Edge Mode DIO 6533 User Manual 5-24 National Instruments Corporation Figure 5-20 shows an input transfer in trailing-edge mode. Figure 5-20. Trailing-Edge Mode Input National Instruments Corporation 5-25 DIO 6533 User Manual Figure5-21 shows a write transfer in trailing edge mode. Figure 5-21. Trailing-Edge Mode Output Trailing-Edge Mode Timing Specifications Figures5-22 and5-23 show the timing diagrams for trailing-edge mode. t Burst Mode t t Burst Mode Timing Specifications Page t t t t t t t t t t t t A Specifications PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices Digital I/O Page Strobed I/O Pattern Generation Page Page Handshaking Pattern and Change Detection Triggers Start and Stop Triggers RTSI Triggers (PCI, PXI, AT) Bus Interfaces Power Requirement Physical Environment B Optional Adapter Description Appendix B Optional Adapter Description Figure B-1. 68-to-50-Pin Adapter Pin Assignments DIO 6533 User Manual B-2 National Instruments Corporation C Customer Communication FTP Support Electronic Services Bulletin Board Support Telephone and Fax Support Telephone Fax Fax-on-Demand Support E-Mail Support (currently U.S. only ) Technical Support Form DIO 6533 Hardware and Software Configuration Form National Instruments Products Other Products Documentation Comment Form Title: Edition Date: Part Number: Mail to: Technical Publications Fax to: Technical Publications Glossary Symbols A B C D E F G H I K L M N O P R S T U V W Page Index Numbers A B C D E F G H I L M N P R S T U