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National Instruments DIO 6533 Timing Connections, Pull-Up and Pull-Down Connections

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Chapter 4 Signal Connections

© National Instruments Corporation 4-13 DIO 6533 User Manual

Strobed applications include digital data acquisition, digital waveform

generation, and data transmission to or from an external device.

Timing Connections

Timing connections include the REQ, ACK (STARTTRIG), and

STOPTRIG pins for pattern generation, and the REQ, ACK, and PCLK

pins for two-way handshaking operation.

The 6533 device provides two handshaking groups, each with its own

timing connections. To perform pattern generation or handshaking, you

must first associate a set of data pins with a group. Do this by assigning

data ports to handshaking groups.

Chapter5, Signal Timing, details the connection and timing of each

pattern generation and handshaking control signal.

Pull-Up and Pull-Down Connections

The CPULL and DPULL lines enable you to select the biasing of the

control and data signals.

If you drive the CPULL pin low, connect the CPULL pin to a GND pin,

or leave the CPULL line disconnected, the 6533 device pulls all its

control lines down to 0V with 2.2kΩ resistors. If you drive the CPULL

pin high or connect the CPULL pin to the +5V pin, the 6533device

pulls all its control lines to +5V with the same 2.2kΩ resistors.

Similarly, if you drive the DPULL pin low, connect the DPULL pin to

a GND pin, or leave the DPULL line disconnected, the 6533 device

pulls all its data lines down to 0V with 100kΩ resistors. If you drive

the DPULL pin high or connect the DPULL pin to the +5V pin, the

6533 device pulls all its control lines to +5V with the same 100kΩ

resistors.

Do not connect CPULL, DPULL, or any other line directly to an

external power supply while the 6533 device is powered off.

The 6533 device drivers power up and reset to high-impedance states.

Therefore, the CPULL and DPULL lines control whether you get high

or low control and data lines, respectively, when you power up the 6533

device or reset its drivers.

Contents

Main Page Important Information Warranty Copyright Trademarks WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS About This Manual Chapter 1 Introduction Chapter 2 Installation and Configuration Chapter 3 Hardware Overview Chapter 4 Signal Connections Chapter 5 Signal Timing Page Table About This Manual Organization of This Manual Conventions Used in This Manual National Instruments Documentation Related Documentation Customer Communication Introduction About the DIO 6533 Devices Using PXI with CompactPCI What You Need to Get Started Software Programming Choices National Instruments Application Software NI-DAQ Driver Software Register-Level Programming Optional Equipment Unpacking Installation and Configuration Software Installation Hardware Installation Installing the PCI-DIO-32HS Installing the PXI-6533 Installing the AT-DIO-32HS Installing the DAQCard-6533 PCI, PXI, and DAQCard Device Configuration AT Device Configuration Bus Interface Plug and Play Mode Switchless Data Acquisition Base I/O Address Selection DMA Channel Selection Interrupt Channel Selection National Instruments Corporation 2-7 DIO 6533 User Manual Table 2-1. PC AT I/O Address Map (Continued) Table 2-2 shows the PC AT interrupt assignments. DIO 6533 User Manual 2-8 National Instruments Corporation Table 2-2. PC AT Interrupt Assignment Map Table 2-1. PC AT I/O Address Map (Continued) National Instruments Corporation 2-9 DIO 6533 User Manual Table 2-3 shows the PC AT 16-bit DMA channel assignments. Note: EISA computers also have channels<0..3> available as 16-bit DMA channels. Table 2-3. PC AT 16-Bit DMA Channel Assignment Map Table 2-2. PC AT Interrupt Assignment Map (Continued) Hardware Overview Figure 3-1. PCI-DIO-32HS/PXI-6533 Block Diagram DIO 6533 User Manual 3-2 National Instruments Corporation Figure 3-2. AT-DIO-32HS Block Diagram National Instruments Corporation 3-3 DIO 6533 User Manual Unstrobed I/O Strobed I/OPattern Generation and Handshaking Pattern and Change Detection Pattern-Detection Triggers Change Detection Message Generation Handshaking Protocols 8255 Emulation Level ACK Leading-Edge Pulse Long Pulse Trailing-Edge Pulse Burst Mode Comparing Protocols Table 3-1. National Instruments Corporation 3-11 DIO 6533 User Manual 6533 Handshaking Protocols Starting a Handshaking Transfer Controlling the Startup Sequence Controlling Line Polarities Transfer Rates Page Signal Connections I/O Connector ! Chapter 4 Signal Connections DIO 6533 User Manual 4-2 National Instruments Corporation Figure 4-1. 6533 Device I/O Connector Pin Assignments Signal Descriptions Page Page Signal Characteristics Control Signal Summary RTSI Bus Interface Board and RTSI Clocks RTSI Triggers Data Signal Connections Unstrobed I/O Chapter 4 Signal Connections Figure 4-3. Example of Data Signal Connections National Instruments Corporation 4-11 DIO 6533 User Manual Strobed I/O Timing Connections Pull-Up and Pull-Down Connections Power Connections ! Field Wiring and Termination Page Page Signal Timing Pattern-Generation Timing Request Timing Internal Requests External Requests t t t t t Trigger Timing t t t t t t Handshake Timing 8255 Emulation Input Output Page 8255 Emulation Mode Timing Specifications t t t t t t t Other Asynchronous Modes Level-ACK Mode Page National Instruments Corporation 5-11 DIO 6533 User Manual Figure5-9 shows an output transfer in level-ACK mode. Figure 5-9. Level-ACK Mode Output Figures5-10 and5-11 show the timing diagrams for level-ACK mode. Level-ACK Mode Timing Specifications Page t t Leading-Edge Mode National Instruments Corporation 5-15 DIO 6533 User Manual Figure 5-12 shows an input transfer in leading-edge mode. Figure 5-12. Leading-Edge Mode Input DIO 6533 User Manual 5-16 National Instruments Corporation Figure5-13 shows an output transfer in leading-edge mode. Figure 5-13. Leading-Edge Mode Output Leading-Edge Mode Timing Specifications Figures5-14 and5-15 show the timing diagrams for leading-edge mode. Page t Long-Pulse Mode DIO 6533 User Manual 5-20 National Instruments Corporation Figure 5-17. Long-Pulse Mode Output Long-Pulse Mode Timing Specifications Figures5-18 and5-19 show the timing diagrams for long-pulse mode. Page t Trailing-Edge Mode DIO 6533 User Manual 5-24 National Instruments Corporation Figure 5-20 shows an input transfer in trailing-edge mode. Figure 5-20. Trailing-Edge Mode Input National Instruments Corporation 5-25 DIO 6533 User Manual Figure5-21 shows a write transfer in trailing edge mode. Figure 5-21. Trailing-Edge Mode Output Trailing-Edge Mode Timing Specifications Figures5-22 and5-23 show the timing diagrams for trailing-edge mode. t Burst Mode t t Burst Mode Timing Specifications Page t t t t t t t t t t t t A Specifications PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices Digital I/O Page Strobed I/O Pattern Generation Page Page Handshaking Pattern and Change Detection Triggers Start and Stop Triggers RTSI Triggers (PCI, PXI, AT) Bus Interfaces Power Requirement Physical Environment B Optional Adapter Description Appendix B Optional Adapter Description Figure B-1. 68-to-50-Pin Adapter Pin Assignments DIO 6533 User Manual B-2 National Instruments Corporation C Customer Communication FTP Support Electronic Services Bulletin Board Support Telephone and Fax Support Telephone Fax Fax-on-Demand Support E-Mail Support (currently U.S. only ) Technical Support Form DIO 6533 Hardware and Software Configuration Form National Instruments Products Other Products Documentation Comment Form Title: Edition Date: Part Number: Mail to: Technical Publications Fax to: Technical Publications Glossary Symbols A B C D E F G H I K L M N O P R S T U V W Page Index Numbers A B C D E F G H I L M N P R S T U