Chapter 5 Signal Timing
© National Instruments Corporation 5-31 DIO 6533 User Manual
Figure 5-27. Burst Mode Input Timing (Default)
Parameter Description Minimum Maximum
Input Parameters
trs Setup time from REQ valid to PCLK 12 —
trh Hold time from PCLK to REQ invalid 0—
t
dis Setup time from input data valid to PCLK 4—
t
dih Hold time from PCLK to input data invalid 6—
Output Parameters
tpc PCLK cycle time 50 7001
tpw PCLK high pulse duration tpc/2 – 5 tpc/2 + 5
tpa PCLK to ACK valid —18
t
ah Hold time from PCLK to ACK invalid 3—
1
tpc = programmable delay from 100 to 700ns, or 50 ns if programmable delay is 0. Timebase
stability for the onboard 20MHz clock source is 50 ppm.
All timing values are in nanoseconds.
PCLK
ACK
Data In
REQ
tdis tdih
trs
tpa
tpw
tpc
trh
tah