Board Features
Analog I/O
DaqBoard/500 Series boards support 16 single-ended or 8 differential analog inputs multiplexed to a 16-bit A/D converter. The input multiplexer is supported by a 176 element channel gain RAM which allows the board to select gain on a per channel basis and to access channels in any order. The 16-bit A/D has a maximum throughput of 200 kHz. An A/D Pacer clock is provided to allow sampling rates from 0.0009 Hz to 200 kHz. The DaqBoard/500 includes two DACs for analog output.*
Digital I/O
DaqBoard/500 Series boards have 24 lines of TTL level digital I/O programmable in three 8-bit ports as either inputs or outputs. All 24 lines are brought out via the main 68-pin SCSI III connector.
Counter 1
Counter 1 (CNTR1) can provide either cumulative or incremental counting capabilities. The counter is capable of counting 5 V LSTTL rising edges to a maximum count of 131071 decimal.
Timer 0 and Timer 1
Timer0 (TMR0) and Timer1 (TMR1) provide a 50% duty cycle square wave 5 V LSTTL output with an output frequency range of 7.7 Hz to 500 kHz. The Timer’s output frequency is based on a 1 MHz oscillation with a divisor of 1 to 65536 decimal.
PCI Interface
DaqBoard/500 Series boards communicate to the PCI bus through an interface controller. The boards are fully plug-and-playand have no switches, potentiometers, or jumpers. The boards feature digitally calibrated A/D and D/A’s, and plug-and-playcompatibility to provide automatic integration into the PC’s configuration when first installed.
The PCI interface provides access to all on-board registers for software configuration of all on-board functions. For maximum performance, the boards feature a 32-bit bus-mastering DMA engine on the ADC and DAC hardware to provide high-speed transfers between the board and system memory.
DMA Engine
Interrupt latency on the PCI bus can be extremely inefficient for high-speed data acquisition. For this reason, DaqBoard/500 and DaqBoard/505 each use an onboard DMA engine. The engine [analogous to the older ISA type DMA controller] supports scatter/gather (buffer chaining) with a pair of chain address registers. These registers point to system memory for use in the buffered transfer.
The DMA controller is loaded with the previously allocated physical addresses of the buffers and only generates interrupt requests when the current transfer buffer has been completed. This reduces the burden of CPU interrupt intervention.
Both analog input and analog output channels* have on-board DMA engine support for high-speed data transfers. The two analog output channels have individual DMA engines and clocking methods available. The DAC1 clocking source may be set to the DAC0 clocking source to allow simultaneous DAC transfers.
All PCI bus transfers are 32-bit operations. Analog input and analog output transfers are each independently software selectable to allow either 16-bit or 32-bit data transfers. An immediate improvement of twice the memory bandwidth can be achieved by transferring two analog input data points [or two analog output data points] into memory as a single 32-bit PCI transfer.
* The DAC analog output channels apply to DaqBoard/500 only.
DaqBoard/500 Series User’s Manual | 947294 | Daq Systems and Device Overviews 1-3 |
