Stopping an ADC Acquisition (CLOCK)
Typical ways of halting an acquisition involve use of one of the following:
oSoftware
oExternal Gate (ADTRGIN) o External Trigger (ADTRGIN)
ADC Software
The acquisition can be stopped by software control.
ADC External Gate
An ADC clock may also be “switched off” with the external trig/gate input (ADTRGIN).
Refer to the section entitled ADC External Gate (on page
ADC External Trigger
The external gate/trig input (ADTRGIN) may also be used to stop an acquisition. In this mode, referred to as ABOUT Trigger Mode, the ADC is disabled after a certain number of conversions are performed following a trigger. The number of conversions may be anywhere from 1 to 65,536, which represents the number of post trigger conversions. Once triggered the ADC Conversion Counter immediately increments after each conversion until it reaches 0, whereupon ADC conversions are automatically disabled. If the timer is loaded with a value of
Note that the Software and External Gate modes described in the section entitled Starting (Triggering) an ADC Acquisition (page
If the External Trigger input is disabled, conversions are enabled as soon as the ADC is enabled and the next valid trigger will enable the internal counter to count conversions. If the External Trigger input is enabled, the first external trigger will start the conversions and the next valid trigger will enable the internal counter to count conversions.
ADC Clock and FIFO Errors
If the ADC is running in DMA operating modes the board will automatically interrupt if clock errors or FIFO overflows become active.
988994 | DaqBoard/500 Series |
