Main
HighWire HW400c/2 User Reference Guide Rev 1.0
October 10, 2006 Copyright 2006, SBE, Inc. Page ii
Revision History
Page
Table of Contents
1 2
3
Page
4
5
Appendix A Appendix B
List of Figures
List of Tables
Page
Page
Conventions
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1
2
2.1 Product Description
HighWire HW400c/2 User Reference Guide Rev 1.0
Figure 1. HW400c/2 Block Diagram
October 10, 2006 Copyright 2006, SBE, Inc. Page 3
2.2 Unpacking Instructions
2.3 Handling Procedures
2.4 Hardware Installation of the HW400c/2
2.5 Returns/Service
2.6 Operating Environment
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2.8 Regulatory Agency Certifications
2.8.1 Safety
2.8.2 US and Canadian Emissions
2.8.3 European Emissions and Immunity
2.9 Agency Compliance
2.10 Physical Properties
2.10.1 HW400c/2 Front Panel
2.10.2 Part number and serial number
.10.3 Bus Keying
2
2.10.4 Power Requirements
2.10.5 Switches
2.10.6 Product Configurations
3
3.1 PowerPC Processor
3.1.1 MPC744X Development/Debug Support
3.1.2 Console port
3.1.3 Pushbutton Reset / Interrupt
Page
3.1.4 COP/JTAG Port
rpose Jumper Block
3.1.5 Special Pu
3.2 MV64462 Sy
3.2.1 System Bu
3.2.2 Dual Data
stem Controller
s
3.2.3 Host PCI B
3.2.4 Local PCI
us
Bus
3.2.5 Serial EEPROM
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Page
3.2.6 MV64462 Ethernet Interface
3.2.7 MV64462 Device Interface
3.2.8 Watchdog Timer
3.2.9 Reset
3.2.10 Multi-Purpose Port (MPP) Usage
3.3 Computer Telephony Bus Controller
3.3.1 H.110 Interface (T8110L)
3.3.2 T8110L Clocking Interface (T8110L)
Page
3.3.3 Operation in Non-H.110 Backplane
3.4 Layer 2 Ethernet Switch
3.4.1 Switch Re 3.4.2 MV64462 S s
3.4.3 Front Panel (RJ-45) Ethernet Interface
gisters Initialization and Monitoring
y tem Controller Ethernet Interface
3ernet Ports .4.4 PT5MC Eth
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3
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3.4.6 On-board Ethernet Indicator LEDs
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3.5 Mezzanine Card Sites
3.5.1 PT5MC Type Mezzanine Cards
2MC Type M
3.5.2 PT ezzanine Cards
3.5.3 PMC Type
3.5.4 Mezzanine Card Power
3.5.5 C Conn r Summ y
PTMC/PM ecto ar
HighWire HW400c/2 User Reference Guide Rev 1.0
3.5.6 PTMC Jn1 and Jn2 PCI Connectors
d IEEE P1386.1. Pn1 32-Bit PCI Pn2 32-Bit PCI
Pin # Signal Name Signal Name Pin
# Pin
# Signal Name Signal Name Pin
3.5.7 PTMC Jn3 CT Bus Connector
Pin # Signal Name Signal Name # # Signal Name Signal Name #
Pin Pin Pin
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.5.8 PTMC Jn4 LAN/User I/O Connector
3
HighWire HW400c/2 User Reference Guide Rev 1.0 Tabl Pn4 PT2MC Pn4 PT5MC
e 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment
October 10, 2006 Copyright 2006, SBE, Inc. Page 37
Pin # Signal Pin Pin Pin
Name Signal Name # # Signal Name Signal Name #
HighWire HW400c/2 User Reference Guide Rev 1.0
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ble 14.
c
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3.6 IPMI System Management
3.6.1 IPMI Controller
3.6.2 Temperatu
re and Voltage Monitor
3.6.3 Hot Swap
3.6.4 Blue (Hot Swap) LED Control 3.6.5 Boot Status Monitor
Ejector Latch Detection
3.6.6 Board Reset via IPMI
3.6.7 IPMI System Power Supply
3.6.8 IPMI Firmw
are EEPROMs
3.6.9 Zircon PM
3.6.10 IMPI Get
Reset
Device ID
3.7 Hot Swap Support
3.7.1 Hot Swap o
3.7.2 Hot Swap on J3
3.7.3 Hot Swap on J4
3.7.4 Hot Swap on J5
3.7.5 Hot Swap Sequence
4
.1 HW400c/2 M
4 emory Map
4.2 CPLD Registers
HighWire HW400c/2 User Reference Guide Rev 1.0
4.2.1 Clock Select Register (CSR)
October 10, 2006 Copyright 2006, SBE, Inc. Page 48
4.2.2 Board Status Register (BSR)
4.2.3 LED Regis
ter A (LEDA)
4.2.4 Memory Option Register (MOR)
4.2.5 Geographi
c Addressing Register (GAR)
4.2.6 PTMC Reset Register (PRR)
4.2.7 PTMC Con
trol Register (PCR)
4.2.8 Board Option Register (BOR)
4.2.9 General Purpose Register (GPR)
4.2.10 PCI Status Register (PSR)
4.2.11 Extended
Type Register (ETR)
4.2.12 Hardware Revision Register (HRR)
4.2.13 PLL Conf uration Re r A
ig giste (PLLA)
4.2.14 PLL Configuration Register B (PLLB)
4.2.15 LED Register B (LEDB)
4.2.16 Device Control Register (DCR)
4.2.17 CPU Timer Register (CTR)
4.2.18 Warm Reset Register (WRR)
4.2.19 SPI Page egister (SP
R R)
4.2.20 SPI Addre
ss Register (SAR)
4.2.21 SPI Read Byte Offset Register (SOR)
4.2.22 Read Byt
e Count Register (RBC)
4.2.23 Write Byte Count Register (WBC)
4.2.24 SPI Data egisters (S S
R DR0 DR7)
4.2.25 SPI Error and Status Register (SESR)
4.2.26 EEPROM ddress (EAR)
A Register
R)
4.2.27 EEPROM Operation/Status Register (EOS
4.2.28 EEPROM Data Registers (EDR0 EDR1)
4.3 Accessing the Serial EEPROM
4.3.1 Reading a
n EEPROM Address
4.3.2 Writing an
4.4 Accessing t
4.4.1 Registers
4.4.2 BCM5388
EEPROM Address
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5388 Register
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5
W400C/2 AND HOST SYSTEM
5.1 Host Hardwa
re and Software Requirements
5.2 Network and System Configuration
5.3 Installing Lin
ux on your host system
5.4 Configuring
5.4.1 Modifying
5.4.2 Configurin
the Host System
the Host Path
5.4.3 Configurin
g Host tftp services
5.4.4 Configuring tftp with inetd
uImage
Page
d 5.4.5 Configuring tftp with xinet
5.4.6 Configuring
a bootp Server
.5 Booting the W400c/2
5 H
5.5.1 U-boot, Universal Bootloader
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Page
Page
5.5.2 Booting with tftp
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HighWire HW400c/2 User Reference Guide Rev 1.0
October 10, 2006 Copyright 2006, SBE, Inc. Page 82
HighWire HW400c/2 User Reference Guide Rev 1.0
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5.5.3 Booting with Disk on Chip
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5.6 Compiling the Kernel (uImage)
5.6.1 Gentoo Application Packages Management
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5.7 Linux Device Drivers
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HighWire HW400c/2 User Reference Guide Rev 1.0
Appendix A
October 10, 2006 Copyright 2006, SBE, Inc. Page 90
Byte offset Description IPMI Definition SBE value Comments
IPMI GetDeviceID
Appendix B
