SMSC LAN8720, LAN8720i 4.3100Base-TXReceive, 4.2.6100M Phase Lock Loop (PLL), 4.3.1100M Receive Input, 4.3.2Equalizer, Baseline Wander Correction and Clock and Data Recovery

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

4.2.6100M Phase Lock Loop (PLL)

„The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter.

				PLL
MAC		Ref_CLK
	RMII 50Mhz by 2 bits		RMII	25MHz	4B/5B	25MHz by	Scrambler
				by 4 bits	Encoder	5 bits	and PISO
	125 Mbps Serial	NRZI	NRZI	MLT-3	MLT-3	Tx
		Converter		Converter		Driver

	Magnetics		RJ45		CAT-5
MLT-3		MLT-3		MLT-3

Figure 4.2 Receive Data Path

4.3100Base-TX Receive

The receive data path is shown in Figure 4.2. Detailed descriptions are given below.

4.3.1100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.

4.3.2Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal.

SMSC LAN8720/LAN8720i	21	Revision 1.0 (05-28-09)
	DATASHEET