Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by some non-IDLE symbol.

5.3.2Collision Detect

A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes inactive during full duplex mode.

COL may be tested by setting register 0, bit 7 high. This enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-asserted within 4 bit times of TXEN falling.

In 10M mode, COL pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de- assertion of TXEN). This is the Signal Quality Error (SQE) signal and indicates that the transmission was successful. The user can disable this pulse by setting bit 11 in register 27.

5.3.3Isolate Mode

The LAN8720 data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic one. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same MII without contention occurring. The transceiver is not isolated on power-up (bit 0:10 = 0).

5.3.4Link Integrity Test

The LAN8720 performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED.

The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using internal signal called DATA_VALID. When DATA_VALID is asserted the control logic moves into a Link-Ready state, and waits for an enable from the Auto Negotiation block. When received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should Auto Negotiation be disabled, the link integrity logic moves immediately to the Link-Up state, when the DATA_VALID is asserted.

Note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic.

5.3.5Power-Down modes

There are 2 power-down modes for the LAN8720 described in the following sections.

Revision 1.0 (05-28-09)

50

SMSC LAN8720/LAN8720i

 

DATASHEET