Manuals / Brands / Computer Equipment / Switch / SMSC / Computer Equipment / Switch

SMSC LAN8720, LAN8720i NAME, MODE, NAME, MODE, NAME, MODE, Table, Table, ADDRESS, DEFAULT, ADDRESS, DEFAULT, ADDRESS, DEFAULT, DESCRIPTION, DESCRIPTION, DESCRIPTION

1 79

Download 79 pages, 1.39 Mb

					Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
							Datasheet
		Table 5.32			Register 27 - Special Control/Status Indications

	ADDRESS	NAME			DESCRIPTION	MODE	DEFAULT

	27.15	AMDIXCTRL		HP Auto-MDIX control		RW	0
				0 - Auto-MDIX enable
				1 - Auto-MDIX disabled (use 27.13 to control channel)

	27.14	Reserved		Reserved		RW	0

	27.13	CH_SELECT		Manual Channel Select		RW	0
				0 - MDI -TX transmits RX receives
				1 - MDIX -TX receives RX transmits

	27.12	Reserved		Write as 0. Ignore on read.		RW	0

	27:11	SQEOFF		Disable the SQE (Signal Quality Error) test		RW,	0
				(Heartbeat):		NASR
				0 - SQE test is enabled.
				1 - SQE test is disabled.

	27.10:5	Reserved		Write as 0. Ignore on read.		RW	000000

	27.4	XPOL		Polarity state of the 10Base-T:		RO	0
				0 - Normal polarity
				1 - Reversed polarity

	27.3:0	Reserved		Reserved		RO	XXXXb

		Table 5.33		Register 28 - Special Internal Testability Controls

	ADDRESS	NAME			DESCRIPTION	MODE	DEFAULT

	28.15:0	Reserved		Do not write to this register. Ignore on read.		RW	N/A

		Table 5.34 Register 29 - Interrupt Source Flags

	ADDRESS	NAME			DESCRIPTION	MODE	DEFAULT

	29.15:8	Reserved		Ignore on read.		RO/	0
						LH

	29.7	INT7		1	= ENERGYON generated	RO/	X
				0	= not source of interrupt	LH

	29.6	INT6		1	= Auto-Negotiation complete	RO/	X
				0	= not source of interrupt	LH

	29.5	INT5		1	= Remote Fault Detected	RO/	X
				0	= not source of interrupt	LH

	29.4	INT4		1	= Link Down (link status negated)	RO/	X
				0	= not source of interrupt	LH

	29.3	INT3		1	= Auto-Negotiation LP Acknowledge	RO/	X
				0	= not source of interrupt	LH

	29.2	INT2		1	= Parallel Detection Fault	RO/	X
				0	= not source of interrupt	LH

Revision 1.0 (05-28-09)	46	SMSC LAN8720/LAN8720i
	DATASHEET

Contents

LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIXSupport PRODUCT FEATURES DATASHEET Table of Contents Page Page List of Figures List of Tables Page Chapter 1 Introduction 1.1General Terms and Conventions 1.2General Description RJ45 Crystal or 1.3Architectural Overview 1.3.1Configuration Figure 1.2 LAN8720/LAN8720i Architectural Overview Chapter 2 Pin Configuration 2.1Package Pin-outDiagram and Signal Table Table 2.1 LAN8720/LAN8720i 24-PINQFN Pinout PIN NO PIN NAME Chapter 3 Pin Description 3.1MAC Interface Signals 3.2LED Signals 3.3Management Signals 3.4General Signals 3.510/100 Line Interface Signals 3.6Analog Reference 3.7Power Signals Chapter 4 Architecture Details 4.1Top Level Functional Architecture 4.2100Base-TXTransmit 4.2.1100M Transmit Data Across the MII/RMII Interface 4.2.24B/5B Encoding 4.2.3Scrambling 4.2.4NRZI and MLT3 Encoding 4.2.5100M Transmit Driver 4.2.6100M Phase Lock Loop (PLL) 4.3100Base-TXReceive 4.3.1100M Receive Input 4.3.2Equalizer, Baseline Wander Correction and Clock and Data Recovery 4.3.3NRZI and MLT-3Decoding 4.3.4Descrambling 4.3.5Alignment 4.3.65B/4B Decoding 4.3.7Receive Data Valid Signal 4.410Base-TTransmit 4.4.110M Transmit Data Across the MII/RMII Interface 4.4.2Manchester Encoding 4.4.310M Transmit Drivers 4.510Base-TReceive 4.5.110M Receive Input and Squelch 4.5.2Manchester Decoding 4.5.310M Receive Data Across the MII/RMII Interface 4.5.4Jabber Detection 4.6MAC Interface 4.6.1RMII 4.7Reference Clock 4.7.1REF_CLK In Mode 4.7.2REF_CLK OUT Mode MAC RMII 10/100 PHY Mag Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal 4.8Auto-negotiation Page 4.8.1Parallel Detection 4.8.2Re-starting Auto-negotiation 4.8.3Disabling Auto-negotiation 4.8.4Half vs. Full Duplex 4.9HP Auto-MDIXSupport 4.10nINTSEL Strapping and LED Polarity Selection 4.11REGOFF and LED Polarity Selection 4.12PHY Address Strapping 4.13Variable Voltage I/O 4.14Transceiver Management Control 4.14.1Serial Management Interface (SMI) Figure 4.10 MDIO Timing and Frame Structure - READ Cycle Figure 4.11 MDIO Timing and Frame Structure - WRITE Cycle Chapter 5 SMI Register Mapping Page Page Page 5.1SMI Register Format Table 5.21 Register 0 - Basic Control ADDRESS DEFAULT Table 5.22 Register 1 - Basic Status Table 5.22 Register 1 - Basic Status (continued) Table 5.23 Register 2 - PHY Identifier Table 5.24 Register 3 - PHY Identifier Table 5.25 Register 4 - Auto Negotiation Advertisement Table 5.25 Register 4 - Auto Negotiation Advertisement (continued) Register 5 - Auto Negotiation Link Partner Ability Table 5.27 Register 6 - Auto Negotiation Expansion Table 5.28 Register 16 - Silicon Revision Table 5.29 Register 17 - Mode Control/Status Table 5.29 Register 17 - Mode Control/Status (continued) Table 5.30 Register 18 - Special Modes Table 5.31 Register 26 - Symbol Error Counter Register 27 - Special Control/Status Indications Register 28 - Special Internal Testability Controls Table 5.34 Register 29 - Interrupt Source Flags Table 5.34 Register 29 - Interrupt Source Flags (continued) Table 5.35 Register 30 - Interrupt Mask Table 5.36 Register 31 - PHY Special Control/Status 5.2Interrupt Management 5.2.1Primary Interrupt System 5.2.2Alternate Interrupt System 5.3Miscellaneous Functions 5.3.1Carrier Sense 5.3.2Collision Detect 5.3.3Isolate Mode 5.3.4Link Integrity Test 5.3.5Power-Downmodes 5.3.6Reset 5.3.7LED Description 5.3.8Loopback Operation XFMR Digital Ethernet Transceiver 10/100 TXD X Digital 5.3.9Configuration Signals Table 5.39 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES MODE[2:0] MODE DEFINITIONS REGISTER Chapter 6 AC Electrical Characteristics 6.1Serial Management Interface (SMI) Timing 6.2RMII 10/100Base-TX/RXTimings (50MHz REF_CLK IN) 6.2.1RMII 100Base-TTX/RX Timings (50MHz REF_CLK IN) CLKIN TXD[1:0] Page Page 6.3RMII 10/100Base-TX/RXTimings (50MHz REF_CLK OUT) 6.3.1RMII 100Base-TTX/RX Timings (50MHz REF_CLK OUT) 6.3.1.2100M RMII Transmit Timing (50MHz REF_CLK OUT) TXD[1:0] Page 6.4RMII CLKIN Requirements 6.5Reset Timing 6.6Clock Circuit Chapter 7 DC Electrical Characteristics 7.1DC Characteristics 7.1.1Maximum Guaranteed Ratings 7.1.2Operating Conditions 7.1.3Power Consumption Table 7.4 Power Consumption Device Only (REF_CLK IN MODE) VDDA3.3 TOTAL POWER CURRENT Page 7.1.4DC Characteristics - Input and Output Buffers Table 7.7 LAN Interface Signals Table 7.8 LED Signals Table 7.9 Configuration Inputs Table 7.10 General Signals Internal Pull-Up / Pull-DownConfigurations Internal Pull-Up / Pull-DownConfigurations (continued) Table 7.12 100Base-TXTransceiver Characteristics Table 7.13 10BASE-TTransceiver Characteristics Chapter 8 Application Notes 8.1Application Diagram 8.1.1RMII Diagram 8.1.2Power Supply Diagram 8.1.3Twisted-PairInterface Diagram 8.2Magnetics Selection Chapter 9 Package Outline Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation Figure 9.2 Reel Dimensions Chapter 10 Revision History