Small Footprint RMII 10/100 Ethernet Transceiver with HP
Datasheet
4.12PHY Address Strapping
The PHY ADDRESS bit is latched into an internal register at the end of a hardware reset. The address bit is input on the RXER/PHYAD0 pin. The default setting is PHYAD0=0 as described in Section 5.3.9.1.
4.13Variable Voltage I/O
The Digital I/O pins on the LAN8720/LAN8720i are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of
4.14Transceiver Management Control
The Management Control module includes 3 blocks:
Serial Management Interface (SMI)
Management Registers Set
Interrupt
4.14.1Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN8720/LAN8720i and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
At the system level there are 2 signals, MDIO and MDC where MDIO is
A special feature (enabled by register 17 bit 3) forces the transceiver to disregard the
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between edges.
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown in Figure 4.10 and Figure 4.11.
The timing relationships of the MDIO signals are further described in Section 6.1, "Serial Management Interface (SMI) Timing," on page 55.
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