Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100.

10/100

TXD

 

 

 

 

 

 

 

TX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ethernet

 

RXD

 

 

 

 

 

 

 

RX

 

MAC

 

 

 

 

 

 

 

 

 

 

 

 

 

Digital

 

 

 

Analog

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SMSC

Ethernet Transceiver

1

2

3

XFMR4

5

6

7

8

RJ45 Loopback Cable.

Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6.

Figure 5.3 Connector Loopback Block Diagram

5.3.9Configuration Signals

The hardware configuration signals are sampled during the power-on sequence to determine the physical address and operating mode.

5.3.9.1Physical Address Bus - PHYAD[0]

The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into an internal register at the end of a hardware reset. In a multi-PHY application (such as a repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each management data frame for a matching address in the relevant bits. When a match is recognized, the PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi- PHY application, this ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the frequency spectrum.

The LAN8720 SMI address may be configured using hardware configuration to either the value 0 or

1.The user can configure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can be written (after SMI communication at some address is established) using the 10/100 Special Modes register (bits18.[4:0]).

The PHYAD0 hardware configuration pin is multiplexed with the RXER pin.

The LAN8720 may be configured to disregard the PHY address in SMI access write by setting the register bit 17.3 (PHYADBP).

5.3.9.2Mode Bus – MODE[2:0]

The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital block is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in Table 5.21, the configuration of the 10/100 digital block is controlled by the register bit values, and the MODE[2:0] pins have no affect.

The LAN8720 mode may be configured using hardware configuration as summarized in Table 5.39. The user may configure the transceiver mode by writing the SMI registers.

SMSC LAN8720/LAN8720i

53

Revision 1.0 (05-28-09)

 

DATASHEET