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| Datasheet |
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| Table 2.1 MII Interface Pins | ||
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| BUFFER |
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NUM PINS | NAME | SYMBOL | TYPE | DESCRIPTION | |
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| Receive Error | RXER | IS | Receive Error: In external PHY mode, the signal |
1 |
| (External |
| (PD) | on this pin is input from the external PHY and |
| PHY Mode) |
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| indicates a receive error in the packet. In internal | |
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| PHY mode, this pin is not used. |
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| Transmit | TXEN | O8 | Transmit Enable: In external PHY mode, this pin |
1 |
| Enable |
| (PD) | output to the external PHY and indicates valid |
| (External |
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| data on TXD[3:0]. In internal PHY mode, this pin | |
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| PHY Mode) |
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| is not used. |
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| Receive Data | RXDV | IS | Receive Data Valid: In external PHY mode, the |
1 |
| Valid |
| (PD) | signal on this pin is input from the external PHY |
| (External |
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| and indicates valid data on RXD[3:0]. In internal | |
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| PHY Mode) |
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| PHY mode, this pin is not used. |
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| Receive | RXCLK | IS | Receive Clock: In external PHY mode, this pin |
1 |
| Clock |
| (PD) | is the receiver clock input from the external PHY. |
| (External |
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| In internal PHY mode, this pin is not used. | |
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| PHY Mode) |
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| Carrier Sense | CRS | IS | Carrier Sense: In external PHY mode, the signal |
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| (External |
| (PD) | on this pin is input from the external PHY and |
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| PHY Mode) |
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| indicates a network carrier. |
1 |
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| General | GPIO3 | IS/O8/ | General Purpose I/O 3 | |
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| Purpose I/O 3 |
| OD8 |
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| (Internal PHY |
| (PU) |
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| Mode Only) |
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| MII Collision | COL | IS | MII Collision Detect: In external PHY mode, the |
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| Detect |
| (PD) | signal on this pin is input from the external PHY |
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| (External |
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| and indicates a collision event. |
1 |
| PHY Mode) |
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| General | GPIO0 | IS/O8/ | General Purpose I/O 0 | |
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| Purpose I/O 0 |
| OD8 |
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| (Internal PHY |
| (PU) |
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| Mode Only) |
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| Management | MDIO | IS/O8 | Management Data: In external PHY mode, this |
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| Data |
| (PD) | pin provides the management data to/from the |
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| (External |
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| external PHY. |
1 |
| PHY Mode) |
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| General | GPIO1 | IS/O8/ | General Purpose I/O 1 | |
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| Purpose I/O 1 |
| OD8 |
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| (Internal PHY |
| (PU) |
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| Mode Only) |
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| Management | MDC | O8 | Management Clock: In external PHY mode, this |
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| Clock |
| (PD) | pin outputs the management clock to the external |
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| (External |
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| PHY. |
1 |
| PHY Mode) |
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| General | GPIO2 | IS/O8/ | General Purpose I/O 2 | |
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| Purpose I/O 2 |
| OD8 |
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| (Internal PHY |
| (PU) |
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| Mode Only) |
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Revision 1.7 | 10 | SMSC LAN9500/LAN9500i |
| DATASHEET |
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