SMSC LAN9500, LAN9500i manual 13

Hi-Speed USB 2.0 to 10/100 Ethernet Controller

Datasheet

Table 2.2 EEPROM Pins

			BUFFER
NUM PINS	NAME	SYMBOL	TYPE	DESCRIPTION
1	EEPROM	EEDI	IS	EEPROM Data In: This pin is driven by the
	Data In		(PD)	EEDO output of the external EEPROM.
	EEPROM	EEDO	O8	EEPROM Data Out: This pin drives the EEDI
	Data Out		(PU)	input of the external EEPROM.
	Auto-MDIX	AUTOMDIX_EN	IS	Auto-MDIX Enable Configuration Strap:
	Enable		(PU)	Determines the default Auto-MDIX setting.
	Configuration			0 = Auto-MDIX is disabled.
	Strap
1				1 = Auto-MDIX is enabled.
				See Note 2.2 for more information on
				configuration straps.
1	EEPROM	EECS	O8	EEPROM chip select: This pin drives the chip
	Chip Select			select output of the external EEPROM.
	EEPROM	EECLK	O8	EEPROM Clock: This pin drives the EEPROM
	Clock		(PD)	clock of the external EEPROM.
	Power Select	PWR_SEL	IS	Power Select Configuration Strap: Determines
	Configuration		(PD)	the default power setting when no EEPROM is
1	Strap			present.
				0 = The LAN9500/LAN9500i is bus powered.
				1 = The LAN9500/LAN9500i is self powered.
				See Note 2.2 for more information on
				configuration straps.

Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load.

Table 2.3 JTAG Pins

			BUFFER
NUM PINS	NAME	SYMBOL	TYPE	DESCRIPTION
	JTAG Test	nTRST	IS	JTAG Test Port Reset (Active-Low): In internal
	Port Reset		(PU)	PHY mode, this pin functions as the JTAG test
	(Internal PHY			port reset input.
1	Mode)
	Receive Data	RXD0	IS	Receive Data 0: In external PHY mode, this pin
	0		(PD)	functions as the receive data 0 input from the
	(External			external PHY.
	PHY Mode)
	JTAG Test	TDO	O8	JTAG Data Output: In internal PHY mode, this
	Data Out			pin functions as the JTAG data output.
	(Internal PHY
1	Mode)
	PHY Reset	nPHY_RST	O8	PHY Reset (Active-Low): In external PHY
	(External			mode, this pin functions as the PHY reset output.
	PHY Mode)

SMSC LAN9500/LAN9500i	13	Revision 1.7 (10-02-08)
	DATASHEET