SMSC LAN9500, LAN9500i manual 17

Hi-Speed USB 2.0 to 10/100 Ethernet Controller

Datasheet

Table 2.6 Ethernet PHY Pins (continued)

			BUFFER
NUM PINS	NAME	SYMBOL	TYPE	DESCRIPTION
	PHY Interrupt	nPHY_INT	O8	PHY Interrupt (Active-Low): In internal PHY
	(Internal PHY			mode, this signal can be configured to output the
	Mode)			internal PHY interrupt signal.
1				Note: The internal PHY interrupt signal is
				active-high.
	PHY Interrupt	nPHY_INT	IS	PHY Interrupt (Active-Low): In external PHY
	(External		(PU)	mode, the signal on this pin is input from the
	PHY Mode)			external PHY and indicates a PHY interrupt has
				occurred.
	+3.3V Analog	VDD33A	P	+3.3V Analog Power Supply
4	Power Supply			Refer to the LAN9500/LAN9500i reference
				schematic for connection information.
	External PHY	EXRES	AI	External PHY Bias Resistor: Used for the
1	Bias Resistor			internal bias circuits. Connect to an external
				12.4K 1.0% resistor to ground.
	Ethernet PLL	VDD18PLL	P	Ethernet PLL +1.8V Power Supply: This pin
	+1.8V Power			must be connected to VDD18CORE for proper
1	Supply			operation.
				Refer to the LAN9500/LAN9500i reference
				schematic for additional connection information.
	Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad
			BUFFER
NUM PINS	NAME	SYMBOL	TYPE	DESCRIPTION
	+3.3V I/O	VDD33IO	P	+3.3V Power Supply for I/O Pins
5	Power			Refer to the LAN9500/LAN9500i reference
				schematic for connection information.
	Digital Core	VDD18CORE	P	Digital Core +1.8V Power Supply Output
2	+1.8V Power			Refer to the LAN9500/LAN9500i reference
	Supply
	Output			schematic for connection information.
Exposed	Ground	VSS	P	Common Ground
pad on
package
bottom
(Figure 2.1)
		Table 2.8 No-Connect Pins
			BUFFER
NUM PINS	NAME	SYMBOL	TYPE	DESCRIPTION
1	No Connect	NC	-	No Connect: These pins must be left floating for
				normal device operation

SMSC LAN9500/LAN9500i	17	Revision 1.7 (10-02-08)
	DATASHEET