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| Datasheet |
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| Table 2.3 JTAG Pins (continued) | ||
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| BUFFER |
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NUM PINS | NAME | SYMBOL | TYPE | DESCRIPTION | |
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| JTAG Test | TCK | IS | JTAG Test Clock: In internal PHY mode, this pin |
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| Clock |
| (PU) | functions as the JTAG test clock. The maximum |
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| (Internal PHY |
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| operating frequency of this clock is 25MHz. |
1 |
| Mode) |
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| Receive Data | RXD1 | IS | Receive Data 1: In external PHY mode, this | |
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| 1 |
| (PD) | signal functions as the receive data 1 input from |
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| (External |
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| the external PHY. |
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| PHY Mode) |
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| JTAG Test | TMS | IS | JTAG Test Mode Select: In internal PHY mode, |
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| Mode Select |
| (PU) | this pin functions as the JTAG test mode select. |
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| (Internal PHY |
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1 |
| Mode) |
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| Receive Data | RXD2 | IS | Receive Data 2: In external PHY mode, this | |
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| 2 |
| (PD) | signal functions as the receive data 2 input from |
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| (External |
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| the external PHY. |
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| PHY Mode) |
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| JTAG Test | TDI | IS | JTAG Data Input: When in internal PHY mode, |
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| Data Input |
| (PU) | this pin functions as the JTAG data input. |
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| (Internal PHY |
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1 |
| Mode) |
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| Receive Data | RXD3 | IS | Receive Data 3: In external PHY mode, this pin | |
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| 3 |
| (PD) | functions as the receive data 3 input from the |
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| external PHY. |
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| PHY Mode) |
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| Table 2.4 Miscellaneous Pins | ||
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| BUFFER |
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NUM PINS | NAME | SYMBOL | TYPE | DESCRIPTION | |
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| PHY Select | PHY_SEL | IS | PHY Select: Selects whether to use the internal |
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| (PD) | Ethernet PHY or the external PHY connected to |
1 |
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| the MII port. |
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| 0 = Internal PHY is used. |
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| 1 = External PHY is used. |
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1 |
| System Reset | nRESET | IS | System Reset |
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| (PU) |
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| Ethernet | nFDX_LED | OD12 | Ethernet |
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| (PU) | Low): This signal is driven low (LED on) when | |
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| Indicator LED |
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| the Ethernet link is operating in |
1 |
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| General | GPIO8 | IS/O12/ | General Purpose I/O 8 | |
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| Purpose I/O 8 |
| OD12 | Note: By default this pin is configured as a |
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| (PU) | |
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| GPIO. | |
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Revision 1.7 | 14 | SMSC LAN9500/LAN9500i |
| DATASHEET |
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