Hi-Speed USB 2.0 to 10/100 Ethernet Controller

Datasheet

Chapter 6 Revision History

Table 6.1 Customer Revision History

REVISION LEVEL

 

 

AND DATE

SECTION/FIGURE/ENTRY

CORRECTION

 

 

 

Rev. 1.6

All

Fixed various typos

(09-09-08)

 

 

 

 

 

 

Table 3.4, “Dump of EEPROM

Fixed typos in example

 

Memory,” on page 23

 

 

 

 

 

Table 3.5, “EEPROM Example -

Fixed typos in example

 

256 Byte EEPROM,” on page 24

 

 

 

 

 

Table 2.4, “Miscellaneous Pins,” on

Added note to GPIO8, GPIO9, and GPIO10 stating

 

page 14

“By default this pin is configured as a GPIO”

 

 

 

Rev. 1.5

All

Fixed various typos

(08-27-08)

 

 

 

Table 4.6, “I/O Buffer

Input leakage and input capacitance values added

 

Characteristics,” on page 31

for IS and IS_5V buffer types.

 

Table 2.1, “MII Interface Pins,” on

Added note to EEP_SIZE pin definition: “A 3-wire

 

page 10

style 1K/2K/4K EEPROM that is organized for 128

 

 

x 8-bit or 256/512 x 8-bit operation must be used.”

 

Chapter 3, "EEPROM Controller

EEPROM Controller section added.

 

(EPC)," on page 20

 

Rev. 1.3

Section 4.3, "Power

Added SUSPEND0 and SUSPEND1 power

(06-30-08)

Consumption," on page 29

consumption tables. Reformatted all power

 

 

consumption tables and added typical values,

 

 

except for customer evaluation board, for which

 

 

maximum value was specified.

Rev. 1.2

Chapter 2, "Pin Description and

Added IS buffer type to following pins when

(06-18-08)

Configuration," on page 9

operating in Internal PHY Mode: RXER, TXEN,

 

 

RXDV, RXCLK, CRS, COL, MDIO, MDC, TXD3,

 

 

TXD2, TXD1, TXD0, TXCLK.

 

Chapter 2, "Pin Description and

Added PD buffer type to following pins when

 

Configuration," on page 9

operating in Internal PHY Mode: TXEN, RXDV,

 

 

COL, MDIO, MDC, TXD3, TXD2, TXD1, TXD0,

 

 

TXCLK.

 

Chapter 2, "Pin Description and

Changed buffer type from PU to PD for following

 

Configuration," on page 9

pins: TXD2 (Internal PHY Mode), TXD1 (Internal

 

 

PHY Mode), TXD0 (Internal PHY Mode).

 

Chapter 2, "Pin Description and

Changed buffer type from PD to PU for following

 

Configuration," on page 9

pins: TXD3 (External PHY Mode).

Rev. 1.2

Table 4.14, “LAN9500/LAN9500i

Changed ESR value from 30 ohms max to 50

(06-16-08)

Crystal Specifications,” on page 39

ohms max.

 

 

 

Rev. 1.2

Table 2.9, “56-QFN Package Pin

Changed pin 33 from “NC” to “TEST3”

(06-10-08)

Assignments,” on page 18

 

 

 

 

 

Table 2.8, “No-Connect Pins,” on

Reduced pin count to one. Removed hidden

 

page 17

TESTMODE entry from the table.

 

 

 

Revision 1.7 (10-02-08)

42

SMSC LAN9500/LAN9500i

 

DATASHEET