Motherboard Description SY-7IS2
9
The SDRAM controller interface is fully configurable through a set
of control registers.
The Intel® 815EP MCH supports industry standard 64-bit wide
DIMMs with SDRAM devices. The thirteen multiplexed address
lines. SMAA[12:0], along with the two bank select lines, SBS[1:0],
allow the Intel® 815EP MCH to support 2M, 4M, 8M, 16M, and
42M x64 DIMM. Only asymmetric addressing is supported. The
Intel® 815EP MCH has 6 SCS# lines (2 copies of each for electrical
loading), enabling the support of up to six 64-bit rows of SDRAM.
The Intel® 815EP MCH targets SDRAM with CL2 and CL3 and
supports both single and double-sided DIMMs. Additionally, the
Intel® 815EP MCH also provides a 1024 deep refresh queue. The
Intel® 815EP MCH can be configured to keep up to 4 page op[en
within the memory array. Pages can be kept open in any one bank of
memory.
SCKE[4:0] is used in configurations requiring powerdown mode for
the SDRAM.
1-6.5 AGP Interface
A single AGP connector is supported by the Intel® 815EP MCH
AGP interface. The AGP buffers operate in one of two selectable
modes in one of two selectable modes in order to support the AGP
Universal Connector:
1) 3.3V drive, not 5 volt safe This mode is compliant to the AGP
1.0 and 2.0 specs.
2) 1.5V drive, not 3.3 volt safe This mode is compliant with the
AGP 2.0 spec.
The following table shows the AGP Data Rate and the Signaling
Levels supported by the MCH:
Signaling Level
Data Rate 1.5V 3.3V
1x AGP Yes Yes
2x AGP Yes Yes
4x AGP Yes No