SOYO SY-7IS2 user manual Chipset Features Setup, Agp

BIOS Setup Utility SY-7IS2

CHIPSET FEATURES SETUP

CHIPSET FEATURES

System BIOS Cacheable

Setting Description Note

Disabled Default

Enabled The ROM area F0000H-FFFFFH is cacheable.

Video BIOS Cacheable

Disabled Default

Enabled The video BIOS C0000H-C7FFFH is cacheable.

Memory Hole At 15M- 16M

Disabled Default

Enabled Some interface cards will map their ROM address to this area. If this occurs, select [Enabled] in this field.

CPU Latency Timer

Disabled

Enabled

When enabled this item, the CPU cycle will only be deferred after it has Default been held in a “Snoop Stall” for 31

clocks and another ADS# has arrived. When disabled, the CPU cycle will be deferred immediately after the MCH receives another ADS#.

Delayed Transaction

Disabled

Enabled

The chipset has an embedded 32-bit

posted write buffer to support delay Default transactions cycles. Select Enabled to support compliance with PCI

specification version 2.1.

AGP

Graphics

Aperture

Size

64MB

32MB

Enabled

Select the size of Accelerated Graphics Default Port (AGP) aperture. The aperture is a

portion of the PCI memory address Default range dedicated for graphics memory address space. Host cycles that hit

the aperture range are forwarded to the AGP without any translation.

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