Sun Microsystems V490 Code Example 6-1POST Error Message, 3POST Diagnostic Running Across FRUs

Here is an excerpt of POST output showing another error message.

0:0>Schizo unit 1 PCI DMA C test 0:0> FAILED

0:0>ERROR: TEST = Schizo unit 1 PCI DMA C test

0:0>H/W under test = Motherboard/Centerplane Schizo 1, I/O Board, CPU 0:0>MSG =

0:0> Schizo Error - 16bit Data miss compare 0:0> address 0000060300012800

0:0> expected 0001020304050607 0:0> observed 0000000000000000 0:0>END_ERROR

CODE EXAMPLE 6-1POST Error Message

Identifying FRUs

An important feature of POST error messages is the H/W under test line. (See the arrow in CODE EXAMPLE 6-1.)

The H/W under test line indicates which FRU or FRUs may be responsible for the error. Note that in CODE EXAMPLE 6-1, three different FRUs are indicated. Using TABLE 6-13to decode some of the terms, you can see that this POST error was most likely caused by a bad system interconnect circuit (Schizo) on the centerplane. However, the error message also indicates that the PCI riser board (I/O board) may be at fault. In the least likely case, the error might stem from the master processor, in this case processor 0.

Why a POST Error May Implicate Multiple FRUs

Because each test operates at such a low level, the POST diagnostics are often more definite in reporting the minute details of the error, like the numerical values of expected and observed results, than they are about reporting which FRU is responsible. If this seems counter-intuitive, consider the block diagram of one data path within a Sun Fire V490 server, shown in FIGURE 6-3.

Processor	Data
	switch

5-way

data

switch

I/O

bridge

PCI

controller

CPU / Memory board

Centerplane

PCI riser board

FIGURE 6-3POST Diagnostic Running Across FRUs

Chapter 6 Diagnostic Tools 81