Appendix B: BIOS POST Codes
B-3
POST Code Description
5Ch Test RAM between 512 and 640 kB
60h Test extended memory
62h Test extended memory address lines
64h Jump to UserPatch1
66h Confi gure advanced cache registers
67h Initialize Multi Proces sor APIC
68h Enable external and CPU cache s
69h Setup System Management Mod e (SMM) area
6Ah Display external L 2 cache size
6Bh Load custom defaults (optional)
6Ch Display shadow-area m essage
70h Display error messag es
72h Check for confi guration errors
76h Check for keyboard errors
7Ch Set up hardware inte rrupt vectors
7Dh Initialize Intelligent System Monitoring (optional)
7Eh Initialize coprocess or if present
80h Disable on board Super I/O ports an d IRQs (optional)
81h Late POST devic e initializ ation
82h Detect and install exter nal RS232 ports
83h Confi gure non-MCD IDE controller s
84h Detect and install extern al parallel ports
85h Initialize P C-compatible PnP ISA devic es
86h Re-ini tialize onboard I/O port s.
87h Confi gure Motherboard Confi gurable Devices (optional)
88h Initialize BIOS Data Area
89h Enable Non-Maskabl e Interrupts (NMIs)
8Ah Initialize Extended BIOS Data Area
8Bh Test and initialize PS/2 mouse
8Ch Initialize fl oppy controller
8Fh Determi ne number of ATA drives (optional)
90h Initialize hard-disk c ontrollers
91h Initialize local-bu s hard-disk controllers
92h Jump to UserPatch2
93h Build MPTABLE for multi- processor boards
95h Install CD ROM for boot
96h Clear huge ES segment register
97h Fix up Multi Processor ta ble
98h 1-2 Search for option ROMs and sha dow if successful. One
long, two short beep s on checksum failure