Design Considerations
PCI Express® takes the best features and ideas behind PCI and combines them with more than 10 years of industry “lessons learned.” The result is a robust, scalable, flexible,
Key Features
•PCI Express architecture is an industry standard
•It is
•Gen I has a scalable bandwidth of 16
•Supports multiple interconnect widths via 1, 2, 4, 8, 12, 16 and 32 lane configura- tions aggregated to match application bandwidth needs.
•Serves new and innovative,
•Delivers unique, advanced features such as Power Management, Quality of Service and other native functions not available in other I/O architectures.
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| PCI Express® | 29 | |||||||||||
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| ➔ | |
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| Device A |
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Device | PCI Express® | Device B |
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Reference Clock | Reference Clock |
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| CPU |
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| PCI Express |
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| PCI Express |
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| Endpoint |
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| Root |
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| PCI Express |
| Complex |
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| Memory |
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| Classifications | ||||||||
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| PCI |
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| • Root Complex | ||||||||
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| Bridge |
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| • Switch | ||||
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| PCI Express |
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| • |
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| Switch |
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| • Bridge | |||||||
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| PCI |
| • Legacy Endpoint | |
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| PCI |
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| • Endpoint | |||
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| Express |
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| PCI |
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| PCI |
| Express |
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| Express |
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| Express |
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| Legacy |
| Legacy |
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| PCI Express |
| PCI Express |
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| Endpoint |
| Endpoint |
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| Endpoint |
| Endpoint |
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PCI Express® topology.
PCI Express
Portfolio
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PCI Express |
| PCI Express |
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| PCI Express |
| PCI Express | ||||||
Bridge |
| Switch |
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| Endpoint |
| PHY | ||||||
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XIO2000A |
| XIO3130 |
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| XIO2200A |
| XIO1100 |
Current TI PCI Express® portfolio.
Texas Instruments 4Q 2006 | Interface Selection Guide |