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Texas Instruments SLVP089 manual 4. Board Layout, Hardware1-5

Models: SLVP089

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Board Layout

1.4 Board Layout

Figure 1–4 shows the SLVP089 board layout.

Figure 1–4. Board Layout

C5 Q1

	C11		R5
C10	C11		R7
		U2	R13
			R13
			C6

CR1

J1	R12	C14
1	CR3	C14
		R6
		R10	JMP1
	R11 CR2			C12	C15
	R11 CR2		R4
TEXAS INSTRUMENTS				R3
				R3	U1

C13

SLVP089

TL5001

+3.3V, 3 AMP

SYNC. RECT BUCK

R8 EVAL BOARD C9 REV2

Hardware1-5

Page 13

Image 13

Texas Instruments SLVP089 manual 4. Board Layout, Hardware1-5

Contents

Mixed-Signal Linear Products ConSLVverterP089SynchronousEvaluationModuleBuckUser’s Guide 199807/98 Printed in U.S.ASLVU001A Literature Number SLVU001A July SLVP089 Synchronous Buck Converter Evaluation Module User’s GuideIMPORTANT NOTICE Read This First How to Use This ManualAbout This Manual Related Documentation From Texas InstrumentsFCC Warning If You Need AssistanceTrademarks 1.1 Introduction 1.2 Schematic 1.3 Input/Output Connections Contents2.1 Introduction 2.2 Operating Specifications 2.3 Design Procedures 2.3.1 Duty Cycle Estimate 2.3.2 Output Filter 2.3.3 Power SwitchTables FiguresChapter HardwarePage TopicFigure 1-1. Typical Synchronous Buck Converter 1.1 IntroductionFigure 1-2. Schematic Diagram 1.2 SchematicHardware SchematicFigure 1-3. Input/Output Connections 1.3 Input/Output ConnectionsInput/Output Connections Figure 1-4. Board Layout 1.4 Board LayoutBoard Layout Hardware1-5Table 1-1. Bill of Materials 1.5 Bill of MaterialsBill of Materials Table 1-2. Line/Load Regulation, 3.3-V Total Variation 1.6 Test ResultsTable 1-3. Load Regulation and Ripple, 3.3-V 9-V Input Figure 1-5. Efficiency Vs LoadFigure 1-7. Power Switch Turn-Off and Delay to Q2 On Figure 1-6. Power Switch Turn-On and Delay from Q2 OffTest Results V CC = 12Test Results Figure 1-8. Inductor and Output RippleHardware1-9 2-ACPage Chapter Design ProcedurePage Topic2.1 Introduction Table 2-1. Operating Specifications 2.2 Operating SpecificationsOperating Specifications Design Procedure2.3.3 Power Switch 2.3 Design Procedures2.3.1 Duty Cycle Estimate 2.3.2 Output Filter2.3.5 Snubber Network 2.3.4 Synchronous Switch and Rectifier+ 3 W 2.3.7 Loop Compensation 2.3.6 Controller Functions1 mA 0.001+ DD V O Figure 2-1. Power Stage Bode PlotFigure 2-2. Compensation Network Figure 2-4. Output Response Figure 2-3. Bode Plot