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Texas Instruments SLVP089 manual 3. Input/Output Connections

Models: SLVP089

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Input/Output Connections

1.3 Input/Output Connections

Figure 1–3 shows the input/output connections to the SLVP089.

Figure 1–3. Input/Output Connections

Power Supply

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			C5	Q1
						Q2
	C11			R5					L1
C10				R7					L1
C10				R7
		U2		R13
				R13
				C6
J1	R12		C14			CR1			J2
J1
1		CR3
1		CR3
				R6					1
				R10	JMP1
						C12			C13
	R11CR2					C12	C15		C8
	R11CR2					R4 R3			C8
TEXAS INSTRUMENTS								R9	SLVP089
TEXAS INSTRUMENTS							U1	R9	SLVP089
			TL5001		C4			R8	EVAL BOARD
			TL5001			C3		C9 REV2
		+3.3V, 3 AMP				C3		C9 REV2
		+3.3V, 3 AMP				R2		C1
		SYNC. RECT BUCK				R2	R1	C1
						C2	R1

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LOAD

Notes: 1) Source power should be able to supply a minimum of 2.5 A at 5.5-V input and/or 1.1-A at 12-V input.

2) Load should be able to sink up to 3A with adequate power rating. Resistive loads with adequate ratings may be used.

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Texas Instruments SLVP089 manual 3. Input/Output Connections

Contents

ConSLVverterP089SynchronousEvaluationModuleBuck Mixed-Signal Linear ProductsUser’s Guide 1998Printed in U.S.A 07/98SLVU001A SLVP089 Synchronous Buck Converter Evaluation Module User’s Guide Literature Number SLVU001A JulyIMPORTANT NOTICE How to Use This Manual Read This FirstAbout This Manual Related Documentation From Texas InstrumentsIf You Need Assistance FCC WarningTrademarks Contents 1.1 Introduction 1.2 Schematic 1.3 Input/Output Connections2.1 Introduction 2.2 Operating Specifications 2.3 Design Procedures 2.3.1 Duty Cycle Estimate 2.3.2 Output Filter 2.3.3 Power SwitchFigures TablesHardware ChapterPage Topic1.1 Introduction Figure 1-1. Typical Synchronous Buck Converter1.2 Schematic Figure 1-2. Schematic DiagramHardware Schematic1.3 Input/Output Connections Figure 1-3. Input/Output ConnectionsInput/Output Connections 1.4 Board Layout Figure 1-4. Board LayoutBoard Layout Hardware1-51.5 Bill of Materials Table 1-1. Bill of MaterialsBill of Materials 1.6 Test Results Table 1-2. Line/Load Regulation, 3.3-V Total VariationTable 1-3. Load Regulation and Ripple, 3.3-V 9-V Input Figure 1-5. Efficiency Vs LoadFigure 1-6. Power Switch Turn-On and Delay from Q2 Off Figure 1-7. Power Switch Turn-Off and Delay to Q2 OnTest Results V CC = 12Figure 1-8. Inductor and Output Ripple Test ResultsHardware1-9 2-ACPage Design Procedure ChapterPage Topic2.1 Introduction 2.2 Operating Specifications Table 2-1. Operating SpecificationsOperating Specifications Design Procedure2.3 Design Procedures 2.3.3 Power Switch2.3.1 Duty Cycle Estimate 2.3.2 Output Filter2.3.4 Synchronous Switch and Rectifier 2.3.5 Snubber Network+ 3 W 2.3.6 Controller Functions 2.3.7 Loop Compensation1 mA 0.001Figure 2-1. Power Stage Bode Plot + DD V OFigure 2-2. Compensation Network Figure 2-3. Bode Plot Figure 2-4. Output Response