Texas Instruments SLVP089 manual + Dd V O

Design Procedures

Calculating the pulse-width-modulator gain as the change in output voltage divided by the change in PWM input voltage gives:

A	PWM	+DDVO		+ 9 – 0	+13.85 Â22.8 db
			VCOMP	1.3 – 0.65

The LC filter has a double pole at:

1￿	+	1		+2.64 kHz
2pLC		2p￿21.6 mH	168 mF

(worst case values) and rolls off at 40-dB per decade after that until the ESR zero is reached at:

	1	+	1		+38 kHz
			2p(0.025)￿210
2pRC				10–6￿

This information is enough to calculate the required compensation values. Figure 2–1 shows the power stage gain and phase plots.

Figure 2–1. Power Stage Bode Plot

FREQUENCY RESPONSE

	50				0
	40				–45
	30				–90
– Solid	20				–135	– Dashed
	10				–180
Gain	0				–225	Phase
	–10				–270
	–20				–315
	–30	102	103	104	–360
	10				105
			Frequency

This response must be corrected by addition of the following:

A pole at zero to give high dc gain

Two zeroes at approximately 2.6 kHz to cancel the LC poles

-A pole at approximately 38 kHz to cancel the ESR zero A final pole to roll off high-frequency gain

The compensation circuit shown in figure 2–2 can be used to implement the above conditions.

Design Procedure 2-7