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Texas Instruments SLVP089 manual 1. Operating Specifications, Design Procedure

Models: SLVP089

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Operating Specifications

2.2 Operating Specifications

Table 2–1 lists the operating specifications for the SLVP089.

Table 2–1. Operating Specifications

Specification	Min	Typ	Max	Units

Input Voltage Range	5.5		12	V
Output Voltage Range	3.10	3.30	3.50	V
Output Current Range	0		3	A
Operating Frequency		100		kHz
Output Ripple			50	mV
Efficiency (Vi = 9 V, IO = 3 A)	85%	90%

Design Procedure

2-3

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Texas Instruments SLVP089 manual 1. Operating Specifications, Design Procedure

Contents

Mixed-Signal Linear Products ConSLVverterP089SynchronousEvaluationModuleBuckUser’s Guide 1998Printed in U.S.A 07/98SLVU001A Literature Number SLVU001A July SLVP089 Synchronous Buck Converter Evaluation Module User’s GuideIMPORTANT NOTICE Read This First How to Use This ManualAbout This Manual Related Documentation From Texas InstrumentsIf You Need Assistance FCC WarningTrademarks 1.1 Introduction 1.2 Schematic 1.3 Input/Output Connections Contents2.1 Introduction 2.2 Operating Specifications 2.3 Design Procedures 2.3.1 Duty Cycle Estimate 2.3.2 Output Filter 2.3.3 Power SwitchTables FiguresChapter HardwarePage TopicFigure 1-1. Typical Synchronous Buck Converter 1.1 IntroductionFigure 1-2. Schematic Diagram 1.2 SchematicHardware Schematic1.3 Input/Output Connections Figure 1-3. Input/Output ConnectionsInput/Output Connections Figure 1-4. Board Layout 1.4 Board LayoutBoard Layout Hardware1-51.5 Bill of Materials Table 1-1. Bill of MaterialsBill of Materials Table 1-2. Line/Load Regulation, 3.3-V Total Variation 1.6 Test ResultsTable 1-3. Load Regulation and Ripple, 3.3-V 9-V Input Figure 1-5. Efficiency Vs LoadFigure 1-7. Power Switch Turn-Off and Delay to Q2 On Figure 1-6. Power Switch Turn-On and Delay from Q2 OffTest Results V CC = 12Test Results Figure 1-8. Inductor and Output RippleHardware1-9 2-ACPage Chapter Design ProcedurePage Topic2.1 Introduction Table 2-1. Operating Specifications 2.2 Operating SpecificationsOperating Specifications Design Procedure2.3.3 Power Switch 2.3 Design Procedures2.3.1 Duty Cycle Estimate 2.3.2 Output Filter2.3.4 Synchronous Switch and Rectifier 2.3.5 Snubber Network+ 3 W 2.3.7 Loop Compensation 2.3.6 Controller Functions1 mA 0.001+ DD V O Figure 2-1. Power Stage Bode PlotFigure 2-2. Compensation Network Figure 2-4. Output Response Figure 2-3. Bode Plot