Texas Instruments SLVP089 manual 2. Compensation Network

Design Procedures

Figure 2–2. Compensation Network

C3

R4

￿

￿

R2

C2

R3

C4

VI

_

VO

Vref

+

The transfer function for this circuit is:

+￿￿fZ1￿￿fZ2

VO

+[1 )sR2(C2 )C3)] [1 )sC4(R3 )R4)]

VI

sC2R4 [1 )sC3R2] [1 )sC4R3]

f ￿￿f ￿￿f

P3

P1 P2

The desired output regulation is ± 6 percent total deviation. The PWM control- ler tolerance is ± 5 percent, and the divider resistors are 1 percent; therefore, the control loop must be very precise. A minimum dc gain of 1000 (60 dB) gives a 0.1 percent tolerance. The integrator (R4, C2) sets the gain of the compensa- tion network. The minimum modulator gain is 18 dB, therefore the compensa- tion network must have a gain of at least 42 dB. With a desired crossover fre- quency of 20 kHz and a desired slope of 20 dB per decade, choose an integra- tor frequency of 2 kHz. This gives a gain of 46 dB at 10 Hz, which is sufficient for this application. If more gain is needed, increase the integrator frequency. R4 is already known, so C2 is calculated as:.

C2 +		1		+	1	+0.034 mF Â0.033 mF
	2p￿f	P1	￿(R4)		2p(2 kHz)(2.32 kW)

Setting fZ2 = 3 kHz to compensate for one of the LC poles gives:

C4 +	1	+		1	+0.023 mF Â0.022 mF
	2p￿f ￿(R4)		2p(3 kHz)(2.32 kW)
	Z2

Now R3 can be calculated using fP 3 (40 kHz), the ESR compensator:

R3 +		1		+	1	+181 WÂ180 W
	2p￿f	P3	￿(C4)		2p(40 kHz)(0.022 mF)

The other LC filter com ensator uses R2 and C2:

R2 +		1		+	1	+1.6 kW
	2p￿f	Z1	￿(C2)		2p(3 kHz)(0.033 mF)

The final rolloff pole (selected at 50 kHz) uses C3 and R2:

C3 +		1		+	1	+0.002 mF Â0.0022 mF
	2p￿f	P2	￿(R2)		2p(50 kHz)(1.6 kW)

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