Conversation Between the TLV1562 and the DSP
7.6Dual Continuous Mode
The dual continuous mode provides a data stream of two input signals. The characteristic of the data protocol is similar to the mono continuous mode but with the use of two RD cycles for one sample/hold cycle.
CAUTION:
In this mode, the sampling result sent out by the ADC is the value of the sample from the last cycle. Therefore, the first sample after initialization is trash.
Table 11. DSP Algorithm for Dual Continuous Mode
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| Wait cycles for the DSP internally (40MHz DSPCLK): | |||||
| STEPS | TIMING, NOTES | APD=0 | APD=0 | APD=1 | APD=1 | ||||||||||
| ADCSYCLK | ADCSYCLK | ADCSYCLK | ADCSYCLK | ||||||||||||
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| = 7.5 MHz | = 10 MHz | = 10 MHz | = 10 MHz | ||
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0. | Initialization |
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| N/A | N/A | ||||||||
| Write all configuration data to the | Activate the dual continuous mode in |
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| N/A | N/A | ||||||||
| ADC | CR0(2;3) |
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1. | Set |
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| deselect ADC |
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| N/A | N/A |
CS |
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2. | Wait for t(SAMPLE1) | t(SAMPLE1) = 100 ns | ≥ | 4 | ≥ | 4 | N/A | N/A | ||||||||
3. | Clear |
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| Select ADC |
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| N/A | N/A | |
CS |
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4. | Clear |
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| Start conversion |
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RD |
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5. | Wait the time tEN(DATAOUT) | tEN(DATAOUT) = 41 ns | ≥ | 2 | ≥ | 2 | N/A | N/A | ||||||||
6. | Read first sample out from the | (Caution: the first result after initialization |
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| N/A | N/A | ||||||||
| data port; reset |
| signal | is trash) |
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| RD |
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7. | Wait for the time t(CONV1) minus | t(CONV1) = 5(6) ADCSysclk; since step 7 | ≥ 23 | ≥ 16 | N/A | N/A | ||||||||||
| step 7 and 8 to ensure 5(6) ADC- | and 8 take at least 4 DSPSYSCLK, the |
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| SYSCLk | calculation are 5(6)ADCSYSCLK minus |
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| 100 ns |
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8. | Clear |
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| Start conversion |
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RD |
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9. | Wait the time tEN(DATAOUT) | tEN(DATAOUT) = 41 ns | ≥ | 2 | ≥ | 2 | N/A | N/A | ||||||||
10. | Read second sample out from the | (Caution: the first result after initialization |
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| N/A | N/A | ||||||||
| data port; reset |
| signal | is trash) |
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| RD |
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11. | Wait for the time t(CONV1) minus | t(CONV1) = 5(6) ADCSysclk; since step 7 | ≥ 23 | ≥ 16 | N/A | N/A | ||||||||||
| step 7 and 8 to ensure 5(6) ADC- | and 8 take at least 4 DSPSYSCLK, the |
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| SYSCLk | calculation are 5(6)ADCSYSCLK minus |
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| 100ns |
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12. | Go to step 4 for more samples |
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| N/A | N/A | ||||||||
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Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP | 17 |