Manual background
; wait for 34 processor cycles
Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP
; wait for 40 clock cycles [t(APDR)=1000ns]

Software Overview

port(DEACTIVE) = @ZERO

; deselect ADC (CS high)

NOP

; wait for tW(CSH)=50ns

* write CR0

 

 

 

port(ADC) = @CR0_SEND

; send CR0 value to the ADC

 

 

 

 

STEP1: port(DEACTIVE) = @ZERO

; deselect ADC (CS high)

NOP

;

 

 

*******************************************

*ADC_dual_IRQ_Start:

*read samples and store them into memory

*******************************************

ADC_dual_IRQ_Start:

ISTEP2: XF

= 0

; clear CSTART

ISTEP3: NOP

 

 

NOP

 

 

NOP

 

; wait for TW(CSTARTL)

.if (AUTO_PWDN_ENABLE)

* wait 800ns before finishing the sampling (requirment in Auto power down mode) repeat(#38)

nop

.endif

ISTEP4: XF

= 1

; set CSTART

STEP5:

.if POLLING_DRV

* wait until

INT– goes low in polling the INT0 pin:

 

= bit(*AR5,15–0)

 

 

 

 

 

 

M1: TC

; test, is the INT0 Bit in IFR=1?

 

 

 

 

 

if (NTC) goto M1

; wait until INT signal went high

 

 

 

 

IFR

= #1

; reset any old interrupt on pin INT0

.elseif INT0_DRIVEN

*user main program area (this could execute additional code)

*go into idle state until the INT0 wakes the processor up

USER_MAIN: IDLE(2)

; the user software could do something else here

goto USER_MAIN

;

.elseif NO_INT0_SIG

*instead of using the INT signal, the processor waits

*for 6ADCSYSCLK+49ns and reads then the sample

repeat(#32) nop

.endif

71

Page 77
Image 77
Texas Instruments TLV1562 Software Overview, if AUTOPWDNENABLE, endif, if POLLINGDRV, = bit*AR5,15-0, elseif INT0DRIVEN