Texas Instruments manual Jumpers Used on the TLV1562EVM, 3-Position Jumpers, 2-Position Jumpers

Operational Overview

3.3.1Jumpers Used on the TLV1562EVM

Table 2. 3-Position Jumpers

JUMPER

GENERAL DESCRIPTION

PIN 1-2

PIN 2-3

W1

Connects BP/CH3 (ADC) to R45 or GND;

Input not in use, grounded to reduce noise

Use as single input channel3 or

differential input positive channel B

W2

Connects BM/CH4 (ADC) to R44 or GND;

Input not in use, grounded to reduce noise

Use as single input channel4 or

differential input negative channel B

W3

Connects

to XF or /RD1

Logic generator is connected to the ADC

DSP is connected to the ADC

RD

W4

+

is connected with DSP_

or

Logic generator is connected to the ADC

DSP is connected to the ADC

WR

WR1

WR

U12-J9/3

W5

The three Jumpers define the prescaling of the

W6

CLKOUT signal to the MCB_CLK Pin, if W8 is

W7

set to Counter-Mode

W8

MCB_CLK is connected to BUFCLK (U14) or

Counter-Mode (MCB_CLK signal is

Counter-Mode disabled (MCB_CLK is

(U11)

divided by the counter, set-up with

synchronize with the CLKOUT signal)

RD1

Jumper W(5-7)

W9

CLK input of the Counter (U2) is connected with

The counter is toggled by the DSP

The counter’s clock is prescaled by two

CLKOUT or CLKOUT/2

system clock (signal BUFF_CLK)

(toggled by half the DSP system clock

(CLKOUT2))

W10

ADC CLKIN is connected to CLK/2 or CLK/4

The ADC clock runs at a quarter of the

The ADC clock runs at half the DSP

DSP clock frequency (10 MHz)

clock frequency (20 MHz)

W11

Connects AP/CH1 (ADC) to R48 or GND;

Input not in use, grounded to reduce

Use as single input channel 1 or

noise

differential input positive channel A

W12

Connects AM/CH2 (ADC) to R47 or GND;

Input not in use, grounded to reduce

Use as single input channel 2 or

noise

differential input negative channel A

W13

Connects REFLO (TLV5651) to Vcc or GND

Disable internal reference

Enable internal reference

W14

Connects SCLK (TLC5618AA) to BCLKX or J8

Normal DSP mode

An external clock source drives the

(BNC)

SCLK pin instead of the DSP

W15

Connects CLK (TLV5651) to CLKOUT (DSP) or

Normal DSP mode

An external clock source drives the CLK

J7 (BNC)

pin instead of the DSP

W23

Connects

to A0, A1, or

A0 and A1 used to generate ADC

signal connects to

pin

CSTART

XF

XF

CSTART

signal

CSTART

W24

Connects DSP_

to

or

ORed with

signal connected to ADC

pin

pin driven by

ORed with

RD

XF

IOSTRB,

XF

RD

RD

IOSTRB

R/W

R/W from the DSP

Table 3. 2-Position Jumpers

JUMPER		GENERAL DESCRIPTION					PINS SHORTED	PINS OPEN
W16	Connects Mode input (TLV 5651) to GND						MODE 0 is chosen (binary data input)	MODE 1 is chosen (2s complement
								data input)
W17	Connects REFIO (TLV5651) to VREF1 or leaves						Use as external reference voltage input	Use as internal reference voltage
	the REFIO pin decoupled to GND via a 0.1 ∝ F							output with this pin terminated into
	capacitor							GND in series with 0.1 pF
W18	Connects DIR (U19) to GND or leaves the DIR						ADC can only write but not read to the data	Normal operation mode
	pin connected to			WR			bus
W19	Connects		(U19) to GND or leaves the			pin	Output driver is isolated and disabled (no	Normal operation mode
		OE			OE
	connected to		CS				signal can bus trough the data bus)
W20	Connects BDX to BDR or leaves BDR open						DSP BDR pin gets a shortcuted feedback	BDR remains open
							from the BDX (transmit) pin; normal mode
W21	Connects BSFX to BSFR or leaves BCLKR open						DSP BSFR pin gets a shortcuted feedback	BSFR remains open
							from the BSFX (transmit) pin; normal mode
W22	Connects BCLKX backwards with BCLKR or						DSP BCLKR pin gets a shortcuted feedback	BCLKR remains open
	leaves it open						from the BCLKX (transmit) pin; normal mode
W28	Connect Sleep input (TLV5651/5 GND						Normal mode of operation	Sleep mode seleted

8SLAA040