Transcend Information TS16GCF600, TS8GCF600 guide

TS8G~16GCF600		600X CompactFlash Card

Ultra DMA Electrical Requirements

Host and Card signal capacitance limits for Ultra DMA operation

The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at 1 MHz.

The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at 1 MHz.

Series termination required for Ultra DMA operation

Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table describes typical values for series termination at the host and the device.

Table: Typical Series Termination for Ultra DMA

Signal	Host Termination		Device Termination
-HIOE (-HDMARDY,HSTROBE)	22 ohm		82 ohm
-IOWR (STOP)	22 ohm		82 ohm
-CS0, -CS1	33 ohm		82 ohm
A00, A01, A02	33 ohm		82 ohm
-DMACK	22 ohm		82 ohm
D15 through D00	33 ohm		33 ohm
DMARQ	82 ohm		22 ohm
INTRQ	82 ohm		22 ohm
IORDY (-DDMARDY, DSTROBE)	82 ohm		22 ohm
-RESET	33 ohm		82 ohm

NOTE Only those signals requiring termination are listed in this table. If a signal is not listed, series termination− is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance.

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Transcend Information TS16GCF600 Ultra DMA Electrical Requirements, Series termination required for Ultra DMA operation

Contents

Power Consumption Dimensions Placement FeaturesDescription Transcend Block Diagram TS8G~16GCF600 Pin Assignments and Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode4 PC Card Memory Mode PC Card I/O Mode Input Leakage Current Input CharacteristicsOutput Drive Type Output Drive Characteristics Output Drive CharacteristicsSymbol Conditions Signal Name Dir Pin Description Signal Description600X CompactFlash Card GND Csel Hstrobe Hdmardy Dir Signal NamePin Description REG ResetDmack Ddmardy IordyDstrobe Electrical Specification Parameter Symbol Input Power Input Characteristics for Udma modeSymbol Output Drive Characteristics for Udma mode Signal Card Host Signal Interface 150 a high state per socket Pull-up pin 45 BVD2 to avoid sensing their batteries as Low Series termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Speed Version 300 ns Symbol Ieee Symbol Min ns Max ns Attribute Memory Read Timing Specification Speed Version 250 ns Symbol Min ns Max ns Table Configuration Register Attribute Memory Write Timing Ieee Common Memory Read Timing SpecificationCycle Time Mode 250 ns 120 ns 100 ns 80 ns Symbol Min Max Symbol Cycle Time Mode 250 ns 120 ns 100 ns 80 ns Common Memory Write Timing Specification Wait Width Time2 TwIORDY TWTLWTH Input Read Timing SpecificationData Delay after Hioe TdHIOE TlGLQV Data Delay from Wait Rising2 TdIORDY TWTHQV Cycle Time Mode 255 ns 120 ns 100 ns 80 ns Output Write Timing Specification Mode True IDE PIO Mode Read/Write Timing SpecificationT6Z TS8G~16GCF600 True IDE Multiword DMA Mode Read/Write Timing Specification TS8G~16GCF600 True IDE Mode Udma True IDE Ultra DMA Mode Read/Write Timing SpecificationPC Card MEM PC Card IO Mode Mode Udma TS8G~16GCF600 Name Name Comment 72.9 50.9 Name Mode Mode4Min Max 14.7 Min Max Name Selected Space Card ConfigurationMultiple Function CompactFlash Storage Cards REG Inpack REG Hiow Wait Hioe CMD Dmardy StrobeDmarq Dmack Stop Hioe DMA Table Attribute Memory Function Attribute Memory FunctionDMA CMD REG Configuration Option Register Base + 00h in Attribute Memory TS8G~16GCF600 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory REG -CE2 Table Pcmcia Mode I/O FunctionTransfer Function DMA CMD Dmarq Dmack Stop Hioe Wait DMA A10 Table PC Card I/O Mode Udma FunctionInpack REG Hiow Wait Hioe CMD A00 CE2 CE1 D15-D8 Common Memory Transfer FunctionTable Common Memory Function DMA REG True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address Configurations Table Contiguous I/O Decoding Contiguous I/O Mapped Addressing Memory Mapped Addressing True IDE Mode Addressing Data Register Address 1F0h170hOffset 0,8,9 CF-ATA Registers Cylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h Offset TS8G~16GCF600 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh Command Code CF-ATA Command Set Definitions Cyl High Cyl Low Sec Num Sec Cnt Feature Check Power Mode 98h or E5hExecute Drive Diagnostic 90h Bit Command Format Track 50h Transcend Information IncErase Sectors C0h Flush Cache E7h Bytes Drive Cyl High Cyl Low Sec Num Sec Cnt FeatureWord Default Total Data Field Type Information Identify Device Ech Ultra DMA Mode Supported and Selected PIO data transfer cycle timing modeCommand sets supported XXXXh Command sets enabled Key management schemes supported Word 0 General ConfigurationCF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode Capability Word 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per Track Current Capacity Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/Track Recommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 68 Minimum PIO transfer cycle time with Iordy Word 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabled Word 89 Time required for Security erase unit completion Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Additional Requirements for CF Advanced Timing Modes Word 160 Power Requirement DescriptionValue Maximum PIO mode timing selected Value Maximum Multiword DMA timing mode supported Current Multiword DMA timing mode selected Value Current PIO timing mode selectedValue Maximum Pcmcia IO timing mode Supported Value Maximum Memory timing mode Supported Value Maximum PC Card Memory Udma timing mode Supported Value Maximum PC Card I/O Udma timing mode SupportedValue PC Card Memory or I/O Udma timing mode Selected Drive Cyl High Cyl Low Sec Num Sec Cnt Idle 97h or E3hIdle Immediate 95h or E1h Initialize Drive Parameters 91h Read Buffer E4h NOP 00hRead DMA C8h Read Long Sector 22h or 23h TS8G~16GCF600 Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS8G~16GCF600 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87h Wear Level F5h Write Buffer E8h Write DMA CAh TS8G~16GCF600 TS8G~16GCF600 BBK UNC Idnf Abrt Amnf Drdy DWF DSC Corr ERR Error PostingNOP S. Table Capacity Transcend Product Capacity CompactFlash Card Ordering Information