Theory of Operation Chapter 6
VXI-MXI User Manual 6-10 © National Instruments Corporation
VXI-MXI
VXI-MXI
VXIbus
Mainframe
#1
VXIbus
Mainframe
#2
MXIbus
VMEbus VMEbus
Slave
Slave
Master
Master
Slave
Slave
Figure 6-2. Deadlock Situation
If the VXI-MXI responds with a VMEbus BERR* to a transfer initiated by a VXIbus device, the
transfer was not completed successfully. The following situations are possible reasons for an
unsuccessful transfer:
• A MXIbus timeout occurred.
• A local timeout occurred.
• A parity error occurred in the address or data portion of the transfer.
• The transfer attempted to access non-existent memory.
• A deadlock condition occurred.
The MXIbus has a built-in block-mode capability for high-speed transfers. VMEbus block-mode
transfers, which are identified by an address modifier code, and which are directed to outward
windows through the VXI-MXI to the MXIbus, are transparently converted into MXIbus block
transfers. Block mode MXIbus operations improve MXIbus performance because a single
address is sent at the beginning of a block-mode cycle. As block-mode transfers can span over
the address range of two MXIbus devices, all MXIbus slave devices are responsible for latching
the initial address broadcast and for generating the successive addresses to determine if any of
the remaining transfers of the block-mode operation are directed to the slave. The amount of
increment between successive addresses depends on whether the block-mode transfer is 8 bits, 16
bits, or 32 bits wide.
MXIbus Slave Mode State Machine
When the VXI-MXI is addressed by a remote MXIbus device, the VXI-MXI translates MXIbus
8-bit, 16-bit, and 32-bit read and write cycles into VMEbus read and write cycles in A16, A24 or
A32 space. The VXI-MXI interface responds to 8-bit or 16-bit reads and writes to onboard
registers located in MXIbus configuration space.
The VXI-MXI is continuously comparing MXIbus addresses and address modifiers to the four
mapping windows. The VXI-MXI only responds to the address modifier codes listed in