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Instructions to Users
Contents
About This Manual
Chapter 1 General Information
Chapter 2 General Description
Chapter 3 Configuration and Installation
Chapter 4 Register Descriptions
Chapter 5 Programming Considerations
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Figures
Tables
About This Manual
Organization of This Manual
How to Use This Manual
Related Documentation
Customer Communication
Chapter 1 General Information
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Overview
Front Panel Features
What Your Kit Should Contain
Optional Equipment
Unpacking
Chapter 2 General
Electrical Characteristics
VMEbus Modules
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VXI-MXI Functional Description
General Description Chapter 2
VXI-MXI User Manual 2-6 National Instruments Corporation
Daughter Card Connection
VXIbus MXIbus
Figure 2-1. VXI-MXI Block Diagram
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Chapter 3 Configuration and Installation
Configuring the VXI-MXI
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The Metal Enclosure
VXIbus Slot 0
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VXIbus Logical Address
VMEbus Request Level
Configuration and Installation Chapter 3
a. Level 3 Requester (default)
b. Level 2 Requester
VXI-MXI User Manual 3-8 National Instruments Corporation
VMEbus Timeout Value
Figure 3-7. VMEbus Timeout Value Selection
VMEbus Timeout Chain Position
W7
VME BTO Chain Position
W7
VME BTO Chain Position
Figure 3-9. VMEbus Timeout; Multiple VXI-MXIs in Mainframe
Configuration and Installation Chapter 3
VXI-MXI User Manual 3-12 National Instruments Corporation
a. Slot 0 VXI-MXI without BTO,
Figure 3-10. No VMEbus Timeout; Multiple VXI-MXIs in Mainframe
b. Non-Slot 0 VXI-MXI without BTO, the VXI-MXI Closest to Slot 0,
d. Non-Slot 0 VXI-MXI without BTO, the VXI-MXI Furthermost from Slot 0,
Interlocked Arbitration Mode
MXIbus System Controller
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MXIbus System Controller Timeout
Figure 3-13. MXIbus System Controller Timeout Value Selection
MXIbus Fairness Option
Fairness Enabled Disabled
CLK10 Source
Chapter 3 Configuration and Installation
Figure 3-15. CLK10 Source Signal Options
National Instruments Corporation 3-19 VXI-MXI User Manual
CLK10 Source Select
W9
W9
CLK10 out SMBCLK10 in from SMB
Chapter 3 Configuration and Installation
Figure 3-17. INTX CLK10 Mapping Switches
National Instruments Corporation 3-21 VXI-MXI User Manual
a. CLK10 Mapping Disabled (Default Setting)
W2
W3 INTX CLK10 Routing
Trigger Input Termination
None
50 Termination
None
50 Termination
Installing the VXI-MXI Hardware
MXIbus Termination
INTX Termination
Installation Instructions
Connecting the INTX Cable
Connecting the MXIbus Cable
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System Power Cycling Requirements
VMEbus Devices in VXIbus/MXIbus Systems
Chapter 4 Register Descriptions
Register Maps
Register Sizes
Register Description Format
Hard and Soft Reset
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Figure 4-1. VXI-MXI Register Map
VXIbus Configuration Registers
VXIbus ID Register
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Device Type Register
VXIbus Status/Control Register
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VXIbus Extender Registers
MODID Register
Logical Address Window Register
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A16 Window Map Register
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A24 Window Map Register
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A32 Window Map Register
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INTX Interrupt Configuration Register (on VXI-MXIs with INTX only)
INTX Trigger Configuration Register (on VXI-MXIs with INTX only)
INTX Utility Configuration Register (on VXI-MXIs with INTX only)
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Subclass Register
MXIbus Defined Registers
MXIbus Status/Control Register
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MXIbus Lock Register
MXIbus IRQ Configuration Register
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Drive Triggers/Read LA Register
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Trigger Mode Selection Register
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Interrupt Status/Control Register
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Status/ID Register
MXIbus Trigger Configuration Register
Trigger Synchronous Acknowledge Register
Trigger Asynchronous Acknowledge Register
IRQ Acknowledge Registers
Chapter 5 Programming Considerations
System Configuration
Planning a VXIbus/MXIbus System Logical Address Map
Level 1 Level 2
Figure 5-1. VXIbus/MXIbus System with Multiframe RM on a PC
Figure 5-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe
Level 1 Level 2
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Figure 5-3. Base and Size Combinations
Figure 5-4. Address Range Allocation for Different Size Values
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MXIbus #1
MXIbus #2
MXIbus #3
Worksheets for Planning Your VXIbus/MXIbus Logical Address Map
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Chapter 5 Programming Considerations
Figure 5-11. Logical Address Map Example with Alternative Worksheet
National Instruments Corporation 5-19 VXI-MXI User Manual
MXI#1
MXI#8
MXI#2
Planning a VXIbus/MXIbus System A16 Address Map
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Worksheets for Planning Your VXIbus/MXIbus A16 Address Map
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Multiframe RM Operation
Configuring the Logical Address Window
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Configuring the A24 and A32 Addressing Windows
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Chapter 6 Theory of Operation
VMEbus Address and Address Modifier Transceivers
VXIbus System Controller Functions
VMEbus Data Transceivers
VMEbus Control Signals Transceivers
VMEbus Requester and Arbiter Circuitry
TTL and ECL Trigger Lines and CLK10 Circuitry
SYSFAIL, ACFAIL, and SYSRESET
Interrupt Circuitry
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Parity Check and Generation
A32, A24, A16, and LA Windows
VXI-MXI Configuration Registers
MXIbus Master Mode State Machine
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MXIbus Slave Mode State Machine
MXIbus Address/Data and Address Modifier Transceivers
MXIbus System Controller Functions
MXIbus Control Signals Transceivers
MXIbus Requester and Arbiter Circuitry
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Appendix A Specifications
Capability Codes
VMEbus
VXIbus
MXIbus
Electrical
Environmental
Physical
Reliability
Requirements
Timing
Master Mode Slave Mode
Appendix B Mnemonics Key
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Appendix C VXI-MXI Component Placement
Removing the Metal Enclosure from the VXI-MXI
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Removing the INTX Daughter Card from the VXI-MXI
Installing the INTX Daughter Card onto the VXI-MXI
Appendix D Connector Descriptions
MXIbus Connector
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INTX Connector
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Appendix E Configuring a Two-Frame System
Configuring VXI-MXIs for a Two-Frame System
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Configuration Requirements for Two-Frame System
BTO Unit
Logical Addresses
CLK10 Mapping
Appendix F Customer Communication
Technical Support Form
VXI-MXI Hardware and Software Configuration Form
National Instruments Products
Other Products
Documentation Comment Form
Glossary
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Symbols
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Index
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