VXI 320222-01 - page 203

Index

© National Instruments Corporation Index-3 VXI-MXI User Manual

BTO. See VME BTO chain position; VME

BTO circuitry.

bus master compliance levels, 2-4

bus slave compliance levels, 2-3

C

cable connections

INTX daughter card, 3-27

MXIbus, 3-28 to 3-30

capability codes

MXIbus, A-2

VMEbus, A-1

VXIbus, A-1

CLK10 circuitry

definition, 2-5

INTX daughter card, 2-9

theory of operation, 6-2 to 6-3

CLK10 source configuration, 3-18 to 3-22

damage warning, 3-22

EXT CLK SMB input/output, 3-20

INTX CLK10 mapping, 3-20 to 3-22

CMODE bit

A16 Window Map Register, 4-14, 4-16

A24 Window Map Register, 4-18, 4-20

A32 Window Map Register, 4-22, 4-24

description, 4-32

Logical Address Window Register,

4-10, 4-12

compliance levels, VMEbus, 2-3 to 2-4

configuration. See also installation; logical

address map configuration; multiframe RM

operation.

A16 register resources, 3-31

CLK10 source, 3-18 to 3-22

EXT CLK SMB input/output, 3-20

INTX CLK10 mapping, 3-20 to 3-22

factory default settings for VXI-MXI

with INTX, 3-3

without INTX, 3-2

interlocked arbitration mode, 3-13 to 3-14

logical address, 3-6 to 3-7

MXIbus fairness option, 3-17

MXIbus System Controller, 3-14 to 3-15

MXIbus System Controller timeout, 3-16

parts locator diagram

VXI-MXI, C-2

VXI-MXI with INTX, 3-3

VXI-MXI without INTX, 3-2

removing metal enclosure, 3-4

reset signal selection, 3-23

Slot 0 settings, 3-4 to 3-5

trigger input termination, 3-22

two-frame system, E-1

VMEbus devices in VXIbus/MXIbus

systems, 3-31

VMEbus request level, 3-7 to 3-8

VMEbus timeout chain position, 3-10

to 3-12

VMEbus timeout value, 3-8 to 3-9

connector descriptions

INTX connector, D-3 to D-4

MXIbus connector, D-1 to D-2

customer communication, xii, F-1

D

daughter card. See INTX daughter card.

deadlock conditions

causes, 3-13

interlocked arbitration mode, 3-13

interrupt circuitry, 6-3

MXIbus master mode state machine, 6-10

DEVCLASS bit, 4-4

Device Type Register, 4-6

DIRQ[7-1] bit, 4-47

documentation

organization, xi

related documentation, xii

Drive Triggers/Read LA Register, 4-39

to 4-40, 6-2

DRVECL0 bit, 4-40

DRVECL1 bit, 4-40

DSYSFAIL bit, 4-33

DSYSRST bit, 4-34

DTACK signal, 3-8, 3-16

DTB arbiter compliance level (PRI), 2-3

DTB requester compliance level (ROR), 2-3

DTRIG[7-0] bit, 4-39

E

ECL trigger lines, 2-5, 6-2 to 6-3

ECL0DIR bit, 4-33

ECL0EN bit, 4-33

ECL1DIR bit, 4-32

ECL1EN bit, 4-32

ECLSTAT0 bit, 4-43

ECLSTAT1 bit, 4-43

EDTYPE bit, 4-7

EINT[7-1]DIR bit, 4-26

EINT[7-1]EN bit, 4-26

electrical specifications, A-2

Contents

Main Page Limited Warranty Copyright Trademarks Warning Regarding Medical and Clinical Use of National Instruments Products FCC/DOC Radio Frequency Interference Compliance Federal Communications Commission Canadian Department of Communications Instructions to Users Contents About This Manual Chapter 1 General Information Chapter 2 General Description Chapter 3 Configuration and Installation Chapter 4 Register Descriptions Chapter 5 Programming Considerations Page Figures Tables About This Manual Organization of This Manual How to Use This Manual Related Documentation Customer Communication Chapter 1 General Information Page Page Overview Front Panel Features What Your Kit Should Contain Optional Equipment Unpacking Chapter 2 General Electrical Characteristics VMEbus Modules Page Page VXI-MXI Functional Description General Description Chapter 2 VXI-MXI User Manual 2-6 National Instruments Corporation Daughter Card Connection VXIbus MXIbus Figure 2-1. VXI-MXI Block Diagram Page Page Page Chapter 3 Configuration and Installation Configuring the VXI-MXI Page Page The Metal Enclosure VXIbus Slot 0 Page VXIbus Logical Address VMEbus Request Level Configuration and Installation Chapter 3 a. Level 3 Requester (default) b. Level 2 Requester VXI-MXI User Manual 3-8 National Instruments Corporation VMEbus Timeout Value Figure 3-7. VMEbus Timeout Value Selection VMEbus Timeout Chain Position W7 VME BTO Chain Position W7 VME BTO Chain Position Figure 3-9. VMEbus Timeout; Multiple VXI-MXIs in Mainframe Configuration and Installation Chapter 3 VXI-MXI User Manual 3-12 National Instruments Corporation a. Slot 0 VXI-MXI without BTO, Figure 3-10. No VMEbus Timeout; Multiple VXI-MXIs in Mainframe b. Non-Slot 0 VXI-MXI without BTO, the VXI-MXI Closest to Slot 0, d. Non-Slot 0 VXI-MXI without BTO, the VXI-MXI Furthermost from Slot 0, Interlocked Arbitration Mode MXIbus System Controller Page MXIbus System Controller Timeout Figure 3-13. MXIbus System Controller Timeout Value Selection MXIbus Fairness Option Fairness Enabled Disabled CLK10 Source Chapter 3 Configuration and Installation Figure 3-15. CLK10 Source Signal Options National Instruments Corporation 3-19 VXI-MXI User Manual CLK10 Source Select W9 W9 CLK10 out SMBCLK10 in from SMB Chapter 3 Configuration and Installation Figure 3-17. INTX CLK10 Mapping Switches National Instruments Corporation 3-21 VXI-MXI User Manual a. CLK10 Mapping Disabled (Default Setting) W2 W3 INTX CLK10 Routing Trigger Input Termination None 50 Termination None 50 Termination Installing the VXI-MXI Hardware MXIbus Termination INTX Termination Installation Instructions Connecting the INTX Cable Connecting the MXIbus Cable Page System Power Cycling Requirements VMEbus Devices in VXIbus/MXIbus Systems Chapter 4 Register Descriptions Register Maps Register Sizes Register Description Format Hard and Soft Reset Page Figure 4-1. VXI-MXI Register Map VXIbus Configuration Registers VXIbus ID Register Page Device Type Register VXIbus Status/Control Register Page VXIbus Extender Registers MODID Register Logical Address Window Register Page Page Page A16 Window Map Register Page Page Page A24 Window Map Register Page Page Page A32 Window Map Register Page Page Page INTX Interrupt Configuration Register (on VXI-MXIs with INTX only) INTX Trigger Configuration Register (on VXI-MXIs with INTX only) INTX Utility Configuration Register (on VXI-MXIs with INTX only) Page Subclass Register MXIbus Defined Registers MXIbus Status/Control Register Page Page Page Page MXIbus Lock Register MXIbus IRQ Configuration Register Page Drive Triggers/Read LA Register Page Trigger Mode Selection Register Page Page Page Interrupt Status/Control Register Page Page Status/ID Register MXIbus Trigger Configuration Register Trigger Synchronous Acknowledge Register Trigger Asynchronous Acknowledge Register IRQ Acknowledge Registers Chapter 5 Programming Considerations System Configuration Planning a VXIbus/MXIbus System Logical Address Map Level 1 Level 2 Figure 5-1. VXIbus/MXIbus System with Multiframe RM on a PC Figure 5-2. VXIbus/MXIbus System with Multiframe RM in a VXIbus Mainframe Level 1 Level 2 Page Figure 5-3. Base and Size Combinations Figure 5-4. Address Range Allocation for Different Size Values Page Page Page Page Page Page MXIbus #1 MXIbus #2 MXIbus #3 Worksheets for Planning Your VXIbus/MXIbus Logical Address Map Page Page Page Page Page Chapter 5 Programming Considerations Figure 5-11. Logical Address Map Example with Alternative Worksheet National Instruments Corporation 5-19 VXI-MXI User Manual MXI#1 MXI#8 MXI#2 Planning a VXIbus/MXIbus System A16 Address Map Page Page Page Page Page Page Page Worksheets for Planning Your VXIbus/MXIbus A16 Address Map Page Page Page Page Page Multiframe RM Operation Configuring the Logical Address Window Page Page Configuring the A24 and A32 Addressing Windows Page Chapter 6 Theory of Operation VMEbus Address and Address Modifier Transceivers VXIbus System Controller Functions VMEbus Data Transceivers VMEbus Control Signals Transceivers VMEbus Requester and Arbiter Circuitry TTL and ECL Trigger Lines and CLK10 Circuitry SYSFAIL, ACFAIL, and SYSRESET Interrupt Circuitry Page Page Parity Check and Generation A32, A24, A16, and LA Windows VXI-MXI Configuration Registers MXIbus Master Mode State Machine Page Page Page MXIbus Slave Mode State Machine MXIbus Address/Data and Address Modifier Transceivers MXIbus System Controller Functions MXIbus Control Signals Transceivers MXIbus Requester and Arbiter Circuitry Page Page Appendix A Specifications Capability Codes VMEbus VXIbus MXIbus Electrical Environmental Physical Reliability Requirements Timing Master Mode Slave Mode Appendix B Mnemonics Key Page G Page O W Appendix C VXI-MXI Component Placement Removing the Metal Enclosure from the VXI-MXI Page Removing the INTX Daughter Card from the VXI-MXI Installing the INTX Daughter Card onto the VXI-MXI Appendix D Connector Descriptions MXIbus Connector Page INTX Connector Page Appendix E Configuring a Two-Frame System Configuring VXI-MXIs for a Two-Frame System Page Page Page Page Configuration Requirements for Two-Frame System BTO Unit Logical Addresses CLK10 Mapping Appendix F Customer Communication Technical Support Form VXI-MXI Hardware and Software Configuration Form National Instruments Products Other Products Documentation Comment Form Glossary ___________________________________________________ Symbols Page Page Page G H K Page N Page Page V W Index Page Page H J N O Page U V