Intel STL2 manual 2 32-bit/33 MHz PCI Subsystem, Network Interface Controller NIC

STL2 Server Board Architecture Overview STL2 Server Board TPS

7.Defaults to Memory Write.

The extensions to memory commands (memory read multiple, memory read line, and memory write and invalidate) work with the cache line size register to give the cache controller advance knowledge of the minimum amount of data to expect. The decision to use either the memory read line or memory read multiple commands is determined by a bit in the configuration space command register for this device.

2.4.1.1.2SCSI Bus

The SCSI data bus is 8 or 16 bits wide with odd parity generated per byte. SCSI control signals are the same for either bus width. To accommodate 8-bit devices on the 16-bit Wide SCSI connector, the AIC-7899 assigns the highest arbitration priority to the low byte of the 16-bit word. This way, 16-bit targets can be mixed with 8-bit if the 8-bit devices are placed on the low data byte. For 8-bit mode, the unused high data byte is self-terminated and does not need to be connected. During chip power-down, all inputs are disabled to reduce power consumption.

2.4.232-bit/33 MHz PCI Subsystem

The 32-bit, 33 MHz, 5V keyed PCI includes the following embedded devices and connectors:

∙Four 32-bit, 33 MHz, 5V keyed PCI expansion slots

∙	Integrated Intel® EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller
	(Intel® 82559 )

∙Integrated ATI Rage* IIC video controller with 4 MB of on-board SGRAM

∙IB6566 South Bridge I/O APIC, PCI-to-ISA bridge, IDE controller, USB controller, and power management.

32-bit PCI features include:

∙Bus speed up to 33 MHz

∙5 V signaling environment

∙Burst transfers up to a peak of 132 MBps

∙8-, 16-, or 32-bit data transfers

∙Plug-and-Play ready

∙Parity enabled

2.4.2.1Network Interface Controller (NIC)

The STL2 server board includes a 10Base-T / 100Base-TX network controller that is based on the Intel® 82559 Fast Ethernet PCI Bus Controller. This device is similar in architecture to its predecessor (Intel® 82558). No external devices are required to implement an embedded network subsystem, other than TX/RX magnetics, two status LEDs, and a connector.

Status LEDs are not included on the external NIC connector, but there is a jumper head (6A) where status LEDs may be connected. The STL2 server board provides the ability to disable the embedded NIC in the BIOS Setup option. When disabled it is not visible to the operating system.

2-10