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STL2 Server Board TPS

Basic Input Output System (BIOS)

∙The system state must be preserved by the user binary (all registers, including extended and MMX, stack contents, and nonuser binary data space, etc.).

∙The user binary code must be relocatable. The user binary is located within the first 1 MB of memory. The user binary code must not make any assumptions about the value of the code segment.

∙The user binary code is always executed from RAM and never from flash.

∙The user binary must not hook critical interrupts, must not reprogram the chip set, and must not take any action that affects the correct functioning of the system BIOS.

∙The user binary ROM must be checksummed. The checksum byte must be placed in the last byte position of the 16K ROM.

The BIOS copies the user binary into system memory before the first scan point. If the user binary reports that it does not contain run time code, it is located in conventional memory (0- 640 KB). Reporting that the user binary has no run time code has the advantage of not using limited option ROM space (therefore, more option ROMs may be executed in a large system configuration). If user binary code is required at run time, it is copied into and executed from option ROM space (0C8000H – 0E7fffH).

At each scan-point during POST, the system BIOS determines if the scan-point has a corresponding user binary entry point to transfer control to the user binary. Presence of a valid entry point in the user binary is determined by examining the bitmap at byte 4 of the user binary header; each entry point has a corresponding “presence” bit in this bitmap. If the bitmap has the appropriate bit set, an entry point ID is placed in the “AL” register and execution is passed to the address computed by (ADR(Byte 5)+5*scan sequence #).

During execution, the user binary may access 11 bytes of extended BIOS data area RAM (EBDA). The segment of EBDA can be found at address 40:0e. Offset 18h through offset 22h is available for the user binary. The BIOS also reserves 8 CMOS bits for the user binary. These bits are in an unchecksummed region of CMOS with default values of zero, and will always be located in the first bank of CMOS. These bits are contiguous, but are not in a fixed location. Upon entry into the user binary, DX contains a ‘token’ that points to the reserved bits. This token is of the following format:

15	12	11

# of bit available –1		Bit offset from start of CMOS of first bit

LSB

The most significant four bits are equal to the number of CMOS bits available minus one. This field is equal to seven, since eight CMOS bits are available. The 12 least significant bits define the position of the CMOS bit in the real-time clock (RTC). This is a bit address rather than a byte address. The CMOS byte location is 1/8th of the 12-bit number, and the remainder is the starting bit position within that byte. For example, if the 12-bit number is 0109h, user binary can use bit 1 of CMOS byte 0108h/8 or 021h. It should be noted that the bits available to the user binary may span more than one byte of CMOS (i.e., a value of 07084h indicates that the upper nibble of byte 10h and the lower nibble of byte 11h are reserved for the user binary).

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STL2 specifications

The Intel STL2, known as the Intel Storage Technology Level 2, is a robust solution designed to elevate storage management and performance for enterprise-level applications. This next-generation system is specifically tailored for organizations that demand high reliability, scalability, and efficiency in their storage solutions.

One of the primary features of the Intel STL2 is its advanced data protection mechanisms. With integrated RAID (Redundant Array of Independent Disks) support, it ensures that data remains safe, even in the event of hardware failure. RAID configurations can be easily set up and managed, allowing businesses to choose the right balance between performance and redundancy based on their unique requirements.

In terms of performance, the STL2 leverages cutting-edge SSD (Solid State Drive) integration to provide high-speed data access and reduced latency. This capability is essential for modern applications that require quick retrieval of large volumes of data, making it suitable for environments like data analytics, AI, and cloud computing.

Scalability is another significant characteristic of the Intel STL2. It is designed to grow alongside an organization’s needs, supporting a diverse range of storage architectures. Whether a company is looking to expand its data center or transition to hybrid cloud solutions, the STL2 can accommodate additional storage resources effortlessly, ensuring that performance does not degrade as storage demands increase.

Moreover, the STL2 features advanced automation and management tools that simplify storage operations. The system allows for real-time monitoring and analytics, providing insights into storage health, performance metrics, and capacity forecasts. This level of visibility enables IT teams to optimize resource utilization and proactively address potential issues before they become critical.

Another notable technology integrated into the STL2 is Intel’s Open Storage Architecture, which promotes interoperability with various software and hardware platforms. This open approach facilitates seamless integrations with existing systems and enhances flexibility within dynamic IT environments.

Lastly, Intel STL2 prioritizes energy efficiency. Its design minimizes power consumption without sacrificing performance, helping organizations reduce their operational costs and carbon footprint.

In summary, the Intel STL2 stands out in the competitive landscape of storage solutions with its focus on data protection, high performance, scalability, advanced management features, open architecture compatibility, and energy efficiency. These characteristics make it an ideal choice for businesses looking to enhance their data storage capabilities in a rapidly evolving digital landscape.