Intel STL2 manual Interrupt Routing, Bios Flash, External Device Connectors, Default I/O Apic

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STL2 Server Board TPS

STL2 Server Board Architecture Overview

2.5.2BIOS Flash

The STL2 baseboard incorporates an Intel® 5V FlashFile™ 28F008SA Flash Memory component. The 28F008SA is a high-performance 8 Mbit memory that is organized as 1 MB of 8 bits each. There are 16 64-KB blocks.

The 8-bit flash memory provides 1024K x 8 of BIOS and nonvolatile storage space. The flash device is directly addressed as 8-bit ISA memory. For more information, see the 5 Volt FlashFile™ Memory (28F008SA x8) Datasheet.

2.5.3External Device Connectors

The external I/O connectors provide support for a PS/2 compatible mouse and keyboard, an SVGA monitor, two serial port connectors, a parallel port connector, a LAN port, and two USB connections.

2.6Interrupt Routing

The STL2 server board interrupt architecture implements two I/O APICs and two PICs through the use of the integrated components in the IB6566 South Bridge component. The STL2 server board interrupt architecture allows first and second PCI interrupts to be mapped to compatible interrupt through the PCI Interrupt Address Index Register (I/O Address 0C00h) in the IB6566 South Bridge.

The STL2 server board supports three interrupt modes:

PIC Mode

Virtual Wire Mode

Symmetric Mode

The IB6566 South Bridge uses integrated logic to map 16 PCI interrupts to EISA/ISA. In default or Extended APIC configurations, each PCI interrupt can be independently routed to one of the 11 EISA interrupts. The interrupt mapping logic for PCI interrupts is disabled when the make bit in the corresponding I/O APIC redirection table entry is disabled (clear). This interrupt routing mechanism allows a clean transition from PIC mode to an APIC during operating system boot.

2.6.1Default I/O APIC

The IB6566 South Bridge integrates a 16-entry I/O APIC which is used to distribute 16 PCI interrupts.

2.6.2Extended I/O APIC

An additional 16-entry I/O APIC is integrated in the IB6566 South Bridge to distribute EISA/ISA interrupts. This additional I/O APIC is enabled only when the IB6566 South Bridge is configured to the Extended APIC configuration.

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Contents Revision September 22 Enterprise Platforms Group STL2 Server BoardDate Revision Modifications Number Revision History STL2 Server Board TPSTable of Contents Jumpers and Connectors Basic Input Output System BiosTable of ContentsSTL2 Server Board TPS STL2 Server Board TPSTable of Contents Power ConsumptionList of Figures STL2 Server Board TPS Embedded NIC PCI SignalsSTL2 Server Board TPS List of Tables List of TablesList of TablesSTL2 Server Board TPS Purpose STL2 Server Board Feature OverviewAudience STL2 Server Board TPS IntroductionIntroduction STL2 Server Board TPS STL2 Server Board Block DiagramSTL2 Server Board Block Diagram This page intentionally left blank Supported Processor Types Intel Pentium III Processor SubsystemSTL2 Server Board Supported Processors Speed FSB Frequency Cache Size CoreDual Processor Operation Processor Bus Termination / Regulation / Power3 PGA370 Socket Termination PackageMemory ServerWorks ServerSet III LE Chipset∙ NB6635 North Bridge 3.0LE ∙ IB6566 South Bridge1 64-bit / 66 MHz PCI Subsystem PCI I/O SubsystemUltra160 / Ultra WideSCSI Controller Be 30 L Command Target Master Embedded Scsi Supported PCI CommandsScsi Transfer Speeds AIC-7899 SupportNetwork Interface Controller NIC 2 32-bit/33 MHz PCI SubsystemSupported Network Features Video Controller Video Controller PCI SignalsBE30L Command Type Target Master Video Controller Supported PCI CommandsResolution Refresh Rate Hz Colors Standard VGA ModesPCI Interface 2.3 IB6566 South BridgeChipset Support Components Power ManagementLegacy I/O Super I/O National* PC97317VUL Compatibility Interrupt ControlPower Management Controller Keyboard and Mouse ConnectorsSerial Ports Parallel PortExternal Device Connectors Bios FlashDefault I/O Apic Interrupt RoutingSTL2 Baseboard Interrupt Routing Diagram PIC mode STL2 Baseboard Interrupt Routing Diagram Symmetric mode PCI Ids Device Bus Number Device Number Slot ID Signal 2316 1511Relationship between PCI IRQ and PCI Device STL2 PCI IDsRevision Page STL2 Server Board TPS Server Management Baseboard Management ControllerServer Management STL2 Server Board TPS Hardware SensorsSensor Number Sensor Type Monitoring Device Sensor Type Sensor-Specific Event Remarks Code Offset PCI Serr EMP AcpiWake On LAN Function AC Link ModeSTL2 Server Board TPS Basic Input Output System Bios Bios OverviewFlash Update Utility System BiosBasic Input Output System Bios STL2 Server Board TPS System Flash ROM LayoutConfiguration Utilities Overview Setup UtilitySetup Utility Operation Setup Utility ScreenKeyboard Command Bar Entering Setup UtilityEnter Execute Command F1 Help← → Select Menu F9 Setup DefaultsF5/- Change Value F6/+ Change ValueMain Menu Selections Main Menu SelectionsSTL2 Server Board TPSBasic Input Output System Bios Processor Settings Submenu SelectionsChoices or Display Feature Only Description User Setting Primary Master and Slave Adapters Submenu SelectionsAdvanced Menu Selections Advanced Menu SelectionsMemory Reconfiruation Submenu Selections Peripheral Configuration Submenu Selections Option ROM Submenu Selections PCI Device Submenu Selections10. Numlock Submenu Selections 11. Security Menu Selections Security Menu SelectionsSystem Hardware Menu Selections 12. Secure Mode Submenu Selections13. Server Menu Selections 14. Wake On Events Submenu Selections16. Boot Menu Selections Boot Menu Selections17. Boot Device Priority Selections 15. Console Redirection Submenu SelectionsExit Menu Selections Cmos Memory Definition18. Hard Drive Selections 19. Removable Devices SelectionsFlash Update Utility Cmos Default OverrideLoading the System Bios OEM Customization User-supplied Bios Code SupportMSB 21. User Binary Area Scan Point Definitions Scan Point DefinitionsScan Point Mask RAM/Stack/BDA Video/Keyboard Language Area Recovery ModeOEM Splash Screen 22. Format of the User Binary Information StructurePost Codes Error Messages and Error Codes23. Port-80h Code Definition Code MeaningBeeps Reason 24. Standard Bios Port-80 CodesPage Revision 25. Recovery Bios Port-80 Codes Post Error Codes and Messages26. Post Error Messages and Codes Basic Input Output System BIOSSTL2 Server Board TPSRevision Beeps Error Cause Recommended Action Bios Revision Level Identification Identifying Bios and BMC Revision LevelsBMC Revision Level Identification Adaptec Scsi Utility Adaptec Scsi Utility Configuration SettingsRunning the Scsi Utility Bus Device Channel Selected Scsi AdapterOption Recommended Setting or User Setting Display Only 27. Adaptec Scsi Utility Setup ConfigurationsExiting Adaptec Scsi Utility This page intentionally left blank Page STL2 Server Board TPS Jumpers and Connectors Jumper and connector location key for FigureBack Panel location key for Figure Jumpers and Connectors STL2 Server Board TPSJumper Blocks Setting CMOS/Password Clear Jumper Block 1J15Jumper Block 1J15 Settings Clearing and Changing a PasswordClearing Cmos Setting Processor Frequency Jumper Block 5E1 Perfoming a Bios Recovery BootJumper Block 5E1 Settings Setting Configuration Jumper Block 1L4Jumper Block 1J15 Default Settings Setting Configuration Jumper Block 6A ConnectorsJumper Block 1L4 Settings Jumper Block 6A SettingsAuxilary ATX Power Connector P34 Main ATX Power Connector P333 I2C Power Connector P37 Processor Connectors P12, P36 System Fan Connectors P29, P27, P11Speaker Connector P31 Speaker Connector P2514. Video Port Connector Pinout Diskette Drive Connector P20Svga Video Port Parallel Port Keyboard and Mouse ConnectorsSerial Ports COM1 and COM2 USB Connectors 13 RJ-45 LAN Connector18. RJ-45 LAN Connector Signals 19. USB ConnectorsUltra160 Scsi Connector P8 Ultra Scsi Connector P920. Ultra Scsi Connector Pinout 21. Ultra160 Scsi Connector22. IDE Connector Pinout IDE Connector P19Jumpers and Connectors STL2 Server Board TPS Pin Signal 23 -Bit PCI Connector Pinout 18 32-Bit PCI Connector24 -Bit PCI Connctor Pinout 19 64-Bit PCI Connector25. Front Panel 24-pin Connector Pinout Front Panel 24-pin Connector Pinout P23Pin Description Jumpers and Connectors STL2 Server Board TPS This page intentionally left blank Page STL2 Server Board Calculated Power Consumption Calculated Power ConsumptionSTL2 Server Board Measured Power Consumption Measured Power ConsumptionPower Consumption STL2 Server Board TPS Devices +5V +12V Total WattageSTL2 Server Board TPS Mechanical Specifications Mechanical SpecificationsMechanical Specifications STL2 Server Board TPS Regulatory Compliance Safety RegulationsRegulation Title Ensure Host Computer and Accessory Module Certifications Installation InstructionsEnsure EMC Place Battery Marking on Computer Prevent Power Supply OverloadEurope United StatesEnvironmental Limits Installation PrecautionsUse Only for Intended Applications System Office EnvironmentSystem Environmental Testing This page intentionally left blank Term Definition STL2 Server Board TPS GlossaryReference Documents STL2 Server Board TPS Reference DocumentsSTL2 Server Board EPS Index IndexIndex STL2 Server Board TPS Revision

STL2 specifications

The Intel STL2, known as the Intel Storage Technology Level 2, is a robust solution designed to elevate storage management and performance for enterprise-level applications. This next-generation system is specifically tailored for organizations that demand high reliability, scalability, and efficiency in their storage solutions.

One of the primary features of the Intel STL2 is its advanced data protection mechanisms. With integrated RAID (Redundant Array of Independent Disks) support, it ensures that data remains safe, even in the event of hardware failure. RAID configurations can be easily set up and managed, allowing businesses to choose the right balance between performance and redundancy based on their unique requirements.

In terms of performance, the STL2 leverages cutting-edge SSD (Solid State Drive) integration to provide high-speed data access and reduced latency. This capability is essential for modern applications that require quick retrieval of large volumes of data, making it suitable for environments like data analytics, AI, and cloud computing.

Scalability is another significant characteristic of the Intel STL2. It is designed to grow alongside an organization’s needs, supporting a diverse range of storage architectures. Whether a company is looking to expand its data center or transition to hybrid cloud solutions, the STL2 can accommodate additional storage resources effortlessly, ensuring that performance does not degrade as storage demands increase.

Moreover, the STL2 features advanced automation and management tools that simplify storage operations. The system allows for real-time monitoring and analytics, providing insights into storage health, performance metrics, and capacity forecasts. This level of visibility enables IT teams to optimize resource utilization and proactively address potential issues before they become critical.

Another notable technology integrated into the STL2 is Intel’s Open Storage Architecture, which promotes interoperability with various software and hardware platforms. This open approach facilitates seamless integrations with existing systems and enhances flexibility within dynamic IT environments.

Lastly, Intel STL2 prioritizes energy efficiency. Its design minimizes power consumption without sacrificing performance, helping organizations reduce their operational costs and carbon footprint.

In summary, the Intel STL2 stands out in the competitive landscape of storage solutions with its focus on data protection, high performance, scalability, advanced management features, open architecture compatibility, and energy efficiency. These characteristics make it an ideal choice for businesses looking to enhance their data storage capabilities in a rapidly evolving digital landscape.