Intel ECB-865 user manual Appendix D Amibios Post Check Point List, Code Description

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User’s Manual

APPENDIX D: AMIBIOS POST Check Point List

AMIBIOS provides all IBM standard Power On Self Test (POST) routines as well as enhanced AMIBIOS POST routines. The POST routines support CPU internal diagnostics. The POST checkpoint codes are accessible via the Manufacturing Test Port (I/O port 80h).

Whenever a recoverable error occurs during the POST, the system BIOS will display an error message describing the message and explaining the problem in detail so that the problem can be corrected.

During the POST, the BIOS signals a checkpoint by issuing one code to I/O address 80H. This code can be used to establish how far the BIOS has executed through the power-on sequence and what test is currently being performed. This is done to help troubleshoot faulty system board.

If the BIOS detects a terminal error condition, it will halt the POST process and attempt to display the checkpoint code written to port 80H. If the system hangs before the BIOS detects the terminal error, the value at port 80H will be the last test performed. In this case, the terminal error cannot be displayed on the screen. The following POST checkpoint codes are valid for all AMIBIOS products with a core BIOS date of 07/15/95 version 6.27 (Enhanced).

Uncompressed Initialization Codes — The uncompressed initialization checkpoint hex codes are listed in order of execution:

 

 

 

 

 

Code

Description

 

 

 

 

 

 

D0

NMI is disabled. CPU ID saved. INIT code checksum verification will

 

 

 

be started.

 

 

D1

Initializing the DMA controller, performing the keyboard controller BAT

 

 

 

test, starting memory refresh, and going to 4GB flat mode.

 

 

D3

To start memory sizing.

 

 

D4

Returning to real mode. Executing any OEM patches and setting the

 

 

 

stack next.

 

 

D5

Passing control to the uncompressed code in shadow RAM at

 

 

 

E000:0000h. The INIT code is copied to segment 0 and control will be

 

 

 

transferred to segment 0.

 

 

D6

Control is in segment 0. Next, checking if <Ctrl><Home> was pressed

 

 

 

and verifying the system BIOS checksum. If either <Ctrl><Home> was

 

 

 

pressed or the system BIOS checksum is bad, next will go to

 

 

 

checkpoint code E0h. Otherwise, going to checkpoint code D7h.

 

 

D7

To pass control to interface module.

 

 

D8

Main BIOS runtime code is to be decompressed.

 

 

D9

Passing control to the main system BIOS in shadow RAM next.

 

 

 

 

 

96ECB-865 User’s Manual

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Contents User’s Manual ECB-865 FCC Statement Disclaimer Copyright NoticeTrademark Acknowledgement Life Support PolicyTechnical Support Evalue Customer ServicesMessage to the Customer Evalue Technology Inc Evalue Europe A/SProduct Warranty Packing List Watchdog Timer Programming Jumper & Connector Manual Objectives IntroductionConnector Definitions Setting JumpersEntering Setup Map Document Amendment History Revision Date CommentManual Objectives Introduction System OverviewSystem Specifications Chipset ITE IT8712F-AExpansion Interface Weight 0.5 Kg Mechanical and EnvironmentalArchitecture Overview 1 82815 Gmch and 82801BA Multiplexed AGP and Display Cache Interface Dram InterfaceAGP Interface 6 USB PCI InterfaceEthernet 7.1 ICH2 LAN Controller ITE IT8712F-A IntelSystems DiskOnChip Installation Procedure Hardware ConfigurationSafety Precautions Removing CPU Main MemoryExpansion Interface Installing the Single Board Computer Installing DOCSystems’ DiskOnChip Flash Disk 1 815E integrated Graphics Controller Drivers Support Disable WDT Watchdog Timer ProgrammingEnable WDT Re-trigger WDTJumper & Connector Jumper & Connector Layout JP10 Jumper & Connector ListJumpers Label Function JP11J11 Connectors Label FunctionJ10 J12Setting Jumpers Clear Cmos JP9 Watchdog Timer Enable / Disable Onboard Watchdog Timer JP12Watchdog Timer Programming I/O Address Select JP6 0553H / 0033H 0543H / 0343HJP10 16 Sec 32 Sec 64 Sec Watchdog Timer Time-Out Interval Select JP10Sec 10.3 COM2 RS-232/422/485 Select JP1, JP2~JP5Proprietary PCI Bus Master Selection JP13 Systems DiskOnChip Memory Address Select JP11Bus Master Keyboard Lock & Power Indicator Connector J3 Connector Definitions System Reset Connector J1External Speaker Connector J2 Primary IDE / Secondary IDE Active Indicator Connector J4Primary IDE Connector J5 Secondary IDE Connector J10 ECB-865 Primary Master connector STROBE, with the PIIX4 latching RESET# Floppy Connector J6 Signal Description Floppy Connector J6 DRVDEN0/1#ATX Power Button Connector J8 Parallel Port Connector J1111.12 DB25 Parallel Port Connector J11 Signal Description Parallel Port Connector J11 STB#GND DTR CTS CTS RTS DSR GND CTS/RTS + CPU Fan and System Fan Connector J14, J25 USB Connector J13, J19Signal Description USB Connector J13, J19 Fast & Standard IrDA Connector J15ATX Power Controller J16 Signal Configuration Fast & Standard IrDA Connector J15Smart Card Interface J17 11.28 10/100 BASE-Tx Ethernet Connector J18, J20 Signal Description 10/100Base-Tx Ethernet Connector J18, J20CRT Connector J22 Signal Description CRT Connector J22Signal Description Int. & PS/2 Keyboard Connector J24, J26 Internal Keyboard Connector J2411.33 PS/2 Keyboard Connector J26 11.35 PS/2 Mouse Connector J26Proprietary PCI Connector J21 Write bursts System Interface Control Error Reporting ArbitrationInterrupts AMI Bios Setup Press F1 to Run Setup or ResumeAMI Bios Setup Main Menu Enter key to accept or enter the sub-menuDate and Time Configuration Cmos Setup Reference TableStandard Cmos Setup Menu Floppy A, Floppy BBoot Sector Virus Protection Master Disk, Slave DiskAdvanced Cmos Setup Defaults Quick BootBootUp Num-Lock 2.2 1st / 2nd / 3rd Boot DeviceTry Other Boot Device Password CheckSystem Bios Cacheable Boot To OS/2Shadow Memory from Address C000~DFFF, 16K Per Segment ICH Delayed Transaction Advanced Chipset Setup DefaultsCPU Ratio Selection Memory Hole Sdram RAS# to CAS# DelayInternal Graphic Mode Select Dram Cycle time SCLKsGreen PC Monitor Power State Power Management Setup DefaultsPower Management/ APM Acpi Aware O/SSuspend Time Out Minute CPU Critical TemperatureStand by Time Out Minute Throttle Slow Clock RatioWake Up on Ring Power Button FunctionWake Up on LAN PCI / Plug and Play Setup Defaults Plug and Play Aware O/SPCI / VGA Palette Snoop PCI Latency Timer PCI ClocksClear Nvram Allocate IRQ to PCI VGAOnBoard Serial Port1 Peripheral Setup DefaultsOnBoard FDC OnBoard Serial Port2On Board Parallel Port DisabledParallel Port Mode 378hParallel Port DMA Channel Parallel Port IRQOn-Chip IDE Hardware Monitor Setup Defaults User’s Manual Driver Installation Driver Installation for Ethernet Adapter WindowsUser’s Manual ECB-865 User’s Manual ECB-865 Windows NT 4.0 Ethernet Installation ECB-865 User’s Manual ECB-865 User’s Manual Driver Installation for Display Adapter Windows User’s Manual ECB-865 User’s Manual ECB-865 Windows NT 4.0 Display Installation ECB-865 User’s Manual ECB-865 Measurement Drawing Appendix a Bios Revisions Bios Rev New Features Bugs/Problems Solved Known ProblemsAppendix B System Resources Memory MapMap Port DescriptionUser’s Manual Interrupt Usage Interrupt DescriptionDMA-channel Usage DMA-channel DescriptionAppendix C Amibios Power-On Self Test If it beeps… Then…Appendix D Amibios Post Check Point List Code DescriptionBios User’s Manual Present User’s Manual ECB-865 User’s Manual