Intel ECB-865 user manual PCI Interface, 6 USB, Ethernet 7.1 ICH2 LAN Controller

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ECB-865

2.3.4PCI Interface

The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH2 requests.

2.3.5IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up 100 Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.

The ICH2’s IDE system contains two independent IDE signal channels. They can be electrically isolated independently. They can be configured to the standard primary and secondary channels (four devices). There are integrated series resistors on the data and control lines.

Access to these controllers is provided by two standard IDC 40-pin connectors.

2.3.6USB

The USB controller provides enhanced support for the Universal Host Controller Interface (UHCI). This includes support that allows legacy software to use a USB-based keyboard and mouse. The ICH2 is USB Revision 1.1 compliant. The ICH2 contains two USB Host Controllers. Each Host Controller includes a root hub with two separate USB ports each, for a total of 4 USB ports. The signals are provided by a 5 x 2 header or an optional USB bracket adapter.

2.3.7Ethernet

2.3.7.1ICH2 LAN Controller

The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed data transfers over the PCI bus. Its bus master capabilities enable the component to process high level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help prevent data under runs and overruns while waiting for bus accesses. This enables the integrated LAN Controller to transmit data with minimum interframe spacing (IFS).

The LAN Controller can operate in either full duplex or half duplex mode. In full duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism.

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Contents User’s Manual ECB-865 FCC Statement Life Support Policy Copyright NoticeTrademark Acknowledgement DisclaimerEvalue Technology Inc Evalue Europe A/S Evalue Customer ServicesMessage to the Customer Technical SupportProduct Warranty Packing List Manual Objectives Introduction Watchdog Timer Programming Jumper & ConnectorConnector Definitions Setting JumpersEntering Setup Map Revision Date Comment Document Amendment HistoryManual Objectives System Overview IntroductionChipset ITE IT8712F-A System SpecificationsExpansion Interface Mechanical and Environmental Weight 0.5 KgArchitecture Overview 1 82815 Gmch and 82801BA Multiplexed AGP and Display Cache Interface Dram InterfaceAGP Interface 6 USB PCI InterfaceEthernet 7.1 ICH2 LAN Controller ITE IT8712F-A IntelSystems DiskOnChip Installation Procedure Hardware ConfigurationSafety Precautions Main Memory Removing CPUExpansion Interface Installing the Single Board Computer Installing DOCSystems’ DiskOnChip Flash Disk 1 815E integrated Graphics Controller Drivers Support Re-trigger WDT Watchdog Timer ProgrammingEnable WDT Disable WDTJumper & Connector Jumper & Connector Layout JP11 Jumper & Connector ListJumpers Label Function JP10J12 Connectors Label FunctionJ10 J11Setting Jumpers 0553H / 0033H 0543H / 0343H Watchdog Timer Enable / Disable Onboard Watchdog Timer JP12Watchdog Timer Programming I/O Address Select JP6 Clear Cmos JP910.3 COM2 RS-232/422/485 Select JP1, JP2~JP5 Watchdog Timer Time-Out Interval Select JP10Sec JP10 16 Sec 32 Sec 64 SecProprietary PCI Bus Master Selection JP13 Systems DiskOnChip Memory Address Select JP11Bus Master Primary IDE / Secondary IDE Active Indicator Connector J4 Connector Definitions System Reset Connector J1External Speaker Connector J2 Keyboard Lock & Power Indicator Connector J3Primary IDE Connector J5 Secondary IDE Connector J10 ECB-865 Primary Master connector STROBE, with the PIIX4 latching RESET# Floppy Connector J6 DRVDEN0/1# Signal Description Floppy Connector J6Parallel Port Connector J11 ATX Power Button Connector J811.12 DB25 Parallel Port Connector J11 STB# Signal Description Parallel Port Connector J11GND DTR CTS CTS RTS DSR GND CTS/RTS + Fast & Standard IrDA Connector J15 USB Connector J13, J19Signal Description USB Connector J13, J19 CPU Fan and System Fan Connector J14, J25ATX Power Controller J16 Signal Configuration Fast & Standard IrDA Connector J15Smart Card Interface J17 Signal Description 10/100Base-Tx Ethernet Connector J18, J20 11.28 10/100 BASE-Tx Ethernet Connector J18, J20Signal Description CRT Connector J22 CRT Connector J2211.35 PS/2 Mouse Connector J26 Internal Keyboard Connector J2411.33 PS/2 Keyboard Connector J26 Signal Description Int. & PS/2 Keyboard Connector J24, J26Proprietary PCI Connector J21 Write bursts System Interface Control Arbitration Error ReportingInterrupts Press F1 to Run Setup or Resume AMI Bios SetupEnter key to accept or enter the sub-menu AMI Bios Setup Main MenuFloppy A, Floppy B Cmos Setup Reference TableStandard Cmos Setup Menu Date and Time ConfigurationMaster Disk, Slave Disk Boot Sector Virus ProtectionQuick Boot Advanced Cmos Setup DefaultsPassword Check 2.2 1st / 2nd / 3rd Boot DeviceTry Other Boot Device BootUp Num-LockSystem Bios Cacheable Boot To OS/2Shadow Memory from Address C000~DFFF, 16K Per Segment ICH Delayed Transaction Advanced Chipset Setup DefaultsCPU Ratio Selection Dram Cycle time SCLKs Sdram RAS# to CAS# DelayInternal Graphic Mode Select Memory HoleAcpi Aware O/S Power Management Setup DefaultsPower Management/ APM Green PC Monitor Power StateThrottle Slow Clock Ratio CPU Critical TemperatureStand by Time Out Minute Suspend Time Out MinuteWake Up on Ring Power Button FunctionWake Up on LAN Plug and Play Aware O/S PCI / Plug and Play Setup DefaultsAllocate IRQ to PCI VGA PCI Latency Timer PCI ClocksClear Nvram PCI / VGA Palette SnoopOnBoard Serial Port2 Peripheral Setup DefaultsOnBoard FDC OnBoard Serial Port1378h DisabledParallel Port Mode On Board Parallel PortParallel Port DMA Channel Parallel Port IRQOn-Chip IDE Hardware Monitor Setup Defaults User’s Manual Driver Installation for Ethernet Adapter Windows Driver InstallationUser’s Manual ECB-865 User’s Manual ECB-865 Windows NT 4.0 Ethernet Installation ECB-865 User’s Manual ECB-865 User’s Manual Driver Installation for Display Adapter Windows User’s Manual ECB-865 User’s Manual ECB-865 Windows NT 4.0 Display Installation ECB-865 User’s Manual ECB-865 Measurement Drawing Bios Rev New Features Bugs/Problems Solved Known Problems Appendix a Bios RevisionsMemory Map Appendix B System ResourcesPort Description MapUser’s Manual Interrupt Description Interrupt UsageDMA-channel Description DMA-channel UsageIf it beeps… Then… Appendix C Amibios Power-On Self TestCode Description Appendix D Amibios Post Check Point ListBios User’s Manual Present User’s Manual ECB-865 User’s Manual