Intel ECB-865 Memory Hole, Dram Cycle time SCLKs, 3.5 CAS# Latency SCLKs, Sdram RAS# Precharge

User’s Manual

4.3.3.3Memory Hole

This option allows the end user to specify the location of a memory hole for memory space requirement from ISA-bus cards.

4.3.3.4DRAM Cycle time (SCLKs)

This option selects the number of SCLKs for an access cycle.

4.3.3.5CAS# Latency (SCLKs)

This option controls the number of SCLKs between the time a read command is sampled by the SDRAM and GMCH 82815E samples corresponding data from the SDRAMs.

4.3.3.6SDRAM RAS# to CAS# Delay

This option controls the number of SCLKs (SDRAM Clock) from a row activate command to a read or write command. If your system installs good quality of SDRAM, you can set this option to “2 SCLKs” to obtain better memory performance. Normally, the option will be set to “3 SCLKs”.

4.3.3.7SDRAM RAS# Precharge

This option controls the number of SCLKs for RAS# precharge. If your system installs good quality of SDRAM, you can set this option to “2 SCLKs” to obtain better memory performance.

4.3.3.8Internal Graphic Mode Select

This option allows the end users to specify the size of video memory shared from system memory.

4.3.3.9USB Function

This option will enable on-chip USB function to support USB (Universal Serial Bus) peripheral devices if user chooses the “Enabled” setting.

58ECB-865 User’s Manual